From: Jacob Lifshay Date: Tue, 24 Nov 2020 02:13:21 +0000 (-0800) Subject: start adding demo of backward-compatible compressed encoding X-Git-Tag: convert-csv-opcode-to-binary~1668 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef62e439925eb3ce5bbc9f36ffa2d51aedeb423b;p=libreriscv.git start adding demo of backward-compatible compressed encoding --- diff --git a/openpower/sv/16_bit_compressed.mdwn b/openpower/sv/16_bit_compressed.mdwn index 943d9de5b..f9f019763 100644 --- a/openpower/sv/16_bit_compressed.mdwn +++ b/openpower/sv/16_bit_compressed.mdwn @@ -628,3 +628,120 @@ the register allocation order in GCC (i.e., it takes the earliest available regi vrsave, vscr (fixed) sfp (fixed) +# Demo of encoding that's backward-compatible with PowerISA v3.1 in both LE and BE mode + +## Assumed instruction encodings for this encoding demo + +Bits numbered using MSB0. Ranges are inclusive. + +### Small Register Field Encoding + +| Encoding | Register | +|----------|----------| +| 0 | R3 | +| 1 | R4 | +| 2 | R5 | +| 3 | R6 | +| 4 | R28 | +| 5 | R29 | +| 6 | R30 | +| 7 | R31 | + +### Instruction Fields + +| Name | Range | Standard | Description | +|------|--------------|---------------|-----------------------------------------------------| +| PO | 0:5 | PowerISA v3.0 | Primary Opcode | +| XO | 21:30 | PowerISA v3.0 | Extended Opcode | +| SCM | 15 | New | Swap between Compressed & standard Mode | +| SCMT | 0 | New | Swap between Compressed & standard Mode Temporarily | +| SI | 16:31 | PowerISA v3.0 | Signed Immediate | +| si0 | prefix 14:31 | PowerISA v3.1 | upper 18 bits Signed Immediate | +| si1 | suffix 16:31 | PowerISA v3.1 | lower 16 bits Signed Immediate | +| SO | 6:8 | New | Small Opcode for 16-bit instructions | +| SOH | 1:5 | New | Small Opcode High bits for 16-bit instructions | +| SRS | 12:14 | New | Small Source Register for 16-bit instructions | +| SRT | 9:11 | New | Small Target Register for 16-bit instructions | + +### Mnemonic Prefixes + +| Prefix | Mode | Next Mode | Next Next Mode | Instruction Width | Example | Comment | +|------------|------------|------------|----------------|-------------------|-------------------------|------------------------------------------------| +| _\_ | Standard | Standard | - | 32-bit | `addi R3, R3, 0x15` | Defined by PowerISA v3.0 | +| `p` | Standard | Standard | - | 64-bit | `paddi R3, R3, 0x12345` | Defined by PowerISA v3.1 | +| `x.` | Standard | Standard | - | 48-bit | `x.placeholder` | `x` means heXa-byte | +| `h.` | Standard | Standard | - | 16-bit | `h.add R3, R4` | `h` means Half-word | +| `hs.` | Standard | Compressed | - | 16-bit | `hs.add R3, R4` | `hs` means Half-word & Swap mode | +| `c.` | Compressed | Compressed | - | 16-bit | `c.addi R3, R4, 0x5` | `c` means Compressed | +| `cs.` | Compressed | Standard | - | 16-bit | `cs.add R3, R4` | `cs` means Compressed & Swap mode | +| `cst.` | Compressed | Standard | Compressed | 16-bit | `cst.add R3, R4` | `cst` means Compressed & Swap mode Temporarily | + +### Standard Mode + +#### Standard Mode 32-bit Instructions (PowerISA v3.0) + +| Mnemonic | PO (0:5) | RT (6:10) | RA (11:15) | SI (16:31) | Operation | +|----------------------|----------|-----------|------------|------------|--------------------------------| +| `addi RT, RA, immed` | 14 | RT | RA | SI | RT <- (RA|0) + EXTS64(SI) | + +#### Standard Mode 64-bit Instructions (PowerISA v3.1) + +Note that bit numbering goes from 0 to 31 in the prefix, then 0 to 31 in the suffix -- following the numbering in the PowerISA v3.1 spec. + +| Field | Value | +|-------------|------------------------------------------------| +| Mnemonic | `paddi RT, RA, immed` | +| PO (0:5) | 14 | +| (6:7) | 2 | +| (8) | 0 | +| (9:10) | // | +| R (11) | 0 | +| (12:13) | // | +| si0 (14:31) | si0 | +| PO (0:5) | 14 | +| RT (6:10) | RT | +| RA (11:15) | RA | +| si1 (16:31) | si1 | +| Operation | RT <- (RA|0) + EXTS64(si0||si1) | + +#### Standard Mode 16-bit Instructions (New) + +| Mnemonic | PO (0:5) | SO (6:8) | SRT (9:11) | SRS (12:14) | SCM (15) | Operation | +|---------------|----------|----------|------------|-------------|----------|---------------------------------------------| +| h.add RT, RS | 5 | 0 | RT | RS | 0 | RT <- RT + RS | +| hs.add RT, RS | 5 | 0 | RT | RS | 1 | RT <- RT + RS
Swap to Compressed Mode | + +#### Standard Mode 48-bit Instructions (New; Placeholder) + +| Mnemonic | PO (0:5) | placeholder (6:20) | XO (21:30) | placeholder (31:47) | Operation | +|---------------|----------|--------------------|------------|---------------------|-------------| +| x.placeholder | 0 | placeholder | != 256 | placeholder | placeholder | + +### Compressed Mode + +#### Compressed Mode 16-bit Instructions (New) + +| Mnemonic | SCMT (0) | SOH (1:5) | SO (6:8) | SRT (9:11) | SRS (12:14) | SCM (15) | Operation | +|----------------|----------|-----------|----------|------------|-------------|----------|---------------------------------------------------------| +| c.add RT, RS | 0 | 1 | 0 | RT | RS | 0 | RT <- RT + RS | +| cs.add RT, RS | 0 | 1 | 0 | RT | RS | 1 | RT <- RT + RS
Swap to Compressed Mode | +| cst.add RT, RS | 1 | 1 | 0 | RT | RS | 1 | RT <- RT + RS
Swap to Compressed Mode Temporarily | + +## LE mode + +TODO(programmerjake): finish + +| Address | Byte | Description | +|---------|------|-------------| +| 0x1000 | | | +| 0x1001 | | | + +## BE mode + +TODO(programmerjake): finish + +| Address | Byte | Description | +|---------|------|-------------| +| 0x1000 | | | +| 0x1001 | | | +