From: Sergiusz Bazanski <q3k@q3k.org>
Date: Tue, 23 Jan 2018 01:15:28 +0000 (+0000)
Subject: Build top module as 'dut' in Verilator and set it as top-level.
X-Git-Tag: 24jan2021_ls180~1742^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef6c517daddf5700b9e35db5664134e39733e615;p=litex.git

Build top module as 'dut' in Verilator and set it as top-level.

When building a design with PicoRV32 we end up with multiple top-level
modules and Verilator becomes confused as to which is the right one.
This change ensures the dut.v generated by the sim build process has
it's top-level name set to 'dut' and that verilator is invoked with this
name.
---

diff --git a/litex/build/sim/core/Makefile b/litex/build/sim/core/Makefile
index 0388cdda..8ccb4ff0 100644
--- a/litex/build/sim/core/Makefile
+++ b/litex/build/sim/core/Makefile
@@ -26,6 +26,7 @@ $(OBJS_SIM): %.o: $(SRC_DIR)/%.c
 sim: mkdir $(OBJS_SIM)
 	verilator -Wno-fatal -O3 --cc dut.v --exe \
 		$(SRCS_SIM_CPP) $(OBJS_SIM) \
+		--top-module dut \
 		-CFLAGS "$(CFLAGS) -I$(SRC_DIR)" \
 		-LDFLAGS "$(LDFLAGS)" \
 		-trace $(INC_DIR)
diff --git a/litex/build/sim/verilator.py b/litex/build/sim/verilator.py
index 312d51e3..d4092b65 100644
--- a/litex/build/sim/verilator.py
+++ b/litex/build/sim/verilator.py
@@ -146,7 +146,7 @@ class SimVerilatorToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        v_output = platform.get_verilog(fragment)
+        v_output = platform.get_verilog(fragment, name=build_name)
         named_sc, named_pc = platform.resolve_signals(v_output.ns)
         v_output.write("dut.v")