From: Marek Olšák Date: Fri, 5 Oct 2012 18:11:15 +0000 (+0200) Subject: r600g: atomize depth-stencil-alpha state X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef723613e017ba33e9d9568ae59eb9faab80aba2;p=mesa.git r600g: atomize depth-stencil-alpha state Reviewed-by: Jerome Glisse --- diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c b/src/gallium/drivers/r600/evergreen_hw_context.c index 93642db3384..f684a5a6cb5 100644 --- a/src/gallium/drivers/r600/evergreen_hw_context.c +++ b/src/gallium/drivers/r600/evergreen_hw_context.c @@ -91,7 +91,6 @@ static const struct r600_reg evergreen_context_reg_list[] = { {R_0286E0_SPI_BARYC_CNTL, 0, 0}, {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0}, {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0}, - {R_028800_DB_DEPTH_CONTROL, 0, 0}, {R_02880C_DB_SHADER_CONTROL, 0, 0}, {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, {R_028844_SQ_PGM_RESOURCES_PS, 0, 0}, @@ -160,7 +159,6 @@ static const struct r600_reg cayman_context_reg_list[] = { {R_0286E0_SPI_BARYC_CNTL, 0, 0}, {R_0286E4_SPI_PS_IN_CONTROL_2, 0, 0}, {R_0286E8_SPI_COMPUTE_INPUT_CNTL, 0, 0}, - {R_028800_DB_DEPTH_CONTROL, 0, 0}, {R_02880C_DB_SHADER_CONTROL, 0, 0}, {R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0, 0}, {R_028840_SQ_PGM_START_PS, REG_FLAG_NEED_BO, 0}, diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 46b2fd780ce..bc3aedb1f1a 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -779,23 +779,20 @@ static void *evergreen_create_blend_state(struct pipe_context *ctx, static void *evergreen_create_dsa_state(struct pipe_context *ctx, const struct pipe_depth_stencil_alpha_state *state) { - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); unsigned db_depth_control, alpha_test_control, alpha_ref; - struct r600_pipe_state *rstate; + struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); if (dsa == NULL) { return NULL; } + r600_init_command_buffer(&dsa->buffer, 3); + dsa->valuemask[0] = state->stencil[0].valuemask; dsa->valuemask[1] = state->stencil[1].valuemask; dsa->writemask[0] = state->stencil[0].writemask; dsa->writemask[1] = state->stencil[1].writemask; - rstate = &dsa->rstate; - - rstate->id = R600_PIPE_STATE_DSA; db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func); @@ -829,8 +826,8 @@ static void *evergreen_create_dsa_state(struct pipe_context *ctx, dsa->alpha_ref = alpha_ref; /* misc */ - r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); - return rstate; + r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control); + return dsa; } static void *evergreen_create_rs_state(struct pipe_context *ctx, @@ -2414,6 +2411,7 @@ void evergreen_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6); r600_init_atom(rctx, &rctx->clip_state.atom, id++, evergreen_emit_clip_state, 26); r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, evergreen_emit_db_misc_state, 7); + r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, evergreen_emit_polygon_offset, 6); r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); r600_init_atom(rctx, &rctx->scissor.atom, id++, evergreen_emit_scissor_state, 4); diff --git a/src/gallium/drivers/r600/r600_blit.c b/src/gallium/drivers/r600/r600_blit.c index 4918c3cb521..102b3808ca2 100644 --- a/src/gallium/drivers/r600/r600_blit.c +++ b/src/gallium/drivers/r600/r600_blit.c @@ -69,7 +69,7 @@ static void r600_blitter_begin(struct pipe_context *ctx, enum r600_blitter_op op util_blitter_save_scissor(rctx->blitter, &rctx->scissor.scissor); util_blitter_save_fragment_shader(rctx->blitter, rctx->ps_shader); util_blitter_save_blend(rctx->blitter, rctx->blend_state.cso); - util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->states[R600_PIPE_STATE_DSA]); + util_blitter_save_depth_stencil_alpha(rctx->blitter, rctx->dsa_state.cso); util_blitter_save_stencil_ref(rctx->blitter, &rctx->stencil_ref.pipe_state); util_blitter_save_sample_mask(rctx->blitter, rctx->sample_mask.sample_mask); } diff --git a/src/gallium/drivers/r600/r600_hw_context.c b/src/gallium/drivers/r600/r600_hw_context.c index 4334f0d3025..015c12abbde 100644 --- a/src/gallium/drivers/r600/r600_hw_context.c +++ b/src/gallium/drivers/r600/r600_hw_context.c @@ -219,7 +219,6 @@ static const struct r600_reg r600_config_reg_list[] = { }; static const struct r600_reg r600_context_reg_list[] = { - {R_028800_DB_DEPTH_CONTROL, 0, 0}, {R_02880C_DB_SHADER_CONTROL, 0, 0}, {GROUP_FORCE_NEW_BLOCK, 0, 0}, {R_028D24_DB_HTILE_SURFACE, 0, 0}, @@ -829,6 +828,8 @@ void r600_begin_new_cs(struct r600_context *ctx) if (ctx->blend_state.cso) ctx->blend_state.atom.dirty = true; + if (ctx->dsa_state.cso) + ctx->dsa_state.atom.dirty = true; if (ctx->rasterizer_state.cso) ctx->rasterizer_state.atom.dirty = true; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index ba1954f5e0f..545441482de 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -178,10 +178,6 @@ static void r600_destroy_context(struct pipe_context *context) if (rctx->blitter) { util_blitter_destroy(rctx->blitter); } - for (int i = 0; i < R600_PIPE_NSTATES; i++) { - free(rctx->states[i]); - } - if (rctx->uploader) { u_upload_destroy(rctx->uploader); } diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index cde12f4df18..144e4674599 100644 --- a/src/gallium/drivers/r600/r600_pipe.h +++ b/src/gallium/drivers/r600/r600_pipe.h @@ -35,7 +35,7 @@ #include "r600_resource.h" #include "evergreen_compute.h" -#define R600_NUM_ATOMS 34 +#define R600_NUM_ATOMS 35 #define R600_MAX_CONST_BUFFERS 2 #define R600_MAX_CONST_BUFFER_SIZE 4096 @@ -160,11 +160,6 @@ struct r600_viewport_state { struct pipe_viewport_state state; }; -enum r600_pipe_state_id { - R600_PIPE_STATE_DSA, - R600_PIPE_NSTATES -}; - struct compute_memory_pool; void compute_memory_pool_delete(struct compute_memory_pool* pool); struct compute_memory_pool* compute_memory_pool_new( @@ -236,8 +231,8 @@ struct r600_blend_state { bool alpha_to_one; }; -struct r600_pipe_dsa { - struct r600_pipe_state rstate; +struct r600_dsa_state { + struct r600_command_buffer buffer; unsigned alpha_ref; ubyte valuemask[2]; ubyte writemask[2]; @@ -415,6 +410,7 @@ struct r600_context { struct r600_clip_misc_state clip_misc_state; struct r600_clip_state clip_state; struct r600_db_misc_state db_misc_state; + struct r600_cso_state dsa_state; struct r600_framebuffer framebuffer; struct r600_poly_offset_state poly_offset_state; struct r600_cso_state rasterizer_state; @@ -484,7 +480,6 @@ struct r600_context { bool streamout_suspended; /* Deprecated state management. */ - struct r600_pipe_state *states[R600_PIPE_NSTATES]; struct r600_range *range; unsigned nblocks; struct r600_block **blocks; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 06f76feb6fb..52441438e88 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -787,23 +787,20 @@ static void *r600_create_blend_state(struct pipe_context *ctx, static void *r600_create_dsa_state(struct pipe_context *ctx, const struct pipe_depth_stencil_alpha_state *state) { - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa); unsigned db_depth_control, alpha_test_control, alpha_ref; - struct r600_pipe_state *rstate; + struct r600_dsa_state *dsa = CALLOC_STRUCT(r600_dsa_state); if (dsa == NULL) { return NULL; } + r600_init_command_buffer(&dsa->buffer, 3); + dsa->valuemask[0] = state->stencil[0].valuemask; dsa->valuemask[1] = state->stencil[1].valuemask; dsa->writemask[0] = state->stencil[0].writemask; dsa->writemask[1] = state->stencil[1].writemask; - rstate = &dsa->rstate; - - rstate->id = R600_PIPE_STATE_DSA; db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) | S_028800_Z_WRITE_ENABLE(state->depth.writemask) | S_028800_ZFUNC(state->depth.func); @@ -836,8 +833,8 @@ static void *r600_create_dsa_state(struct pipe_context *ctx, dsa->sx_alpha_test_control = alpha_test_control & 0xff; dsa->alpha_ref = alpha_ref; - r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control); - return rstate; + r600_store_context_reg(&dsa->buffer, R_028800_DB_DEPTH_CONTROL, db_depth_control); + return dsa; } static void *r600_create_rs_state(struct pipe_context *ctx, @@ -2164,6 +2161,7 @@ void r600_init_state_functions(struct r600_context *rctx) r600_init_atom(rctx, &rctx->clip_misc_state.atom, id++, r600_emit_clip_misc_state, 6); r600_init_atom(rctx, &rctx->clip_state.atom, id++, r600_emit_clip_state, 26); r600_init_atom(rctx, &rctx->db_misc_state.atom, id++, r600_emit_db_misc_state, 4); + r600_init_atom(rctx, &rctx->dsa_state.atom, id++, r600_emit_cso_state, 0); r600_init_atom(rctx, &rctx->poly_offset_state.atom, id++, r600_emit_polygon_offset, 6); r600_init_atom(rctx, &rctx->rasterizer_state.atom, id++, r600_emit_cso_state, 0); r600_init_atom(rctx, &rctx->scissor.atom, id++, r600_emit_scissor_state, 4); diff --git a/src/gallium/drivers/r600/r600_state_common.c b/src/gallium/drivers/r600/r600_state_common.c index 18e8fc523bd..8f9f19b05fd 100644 --- a/src/gallium/drivers/r600/r600_state_common.c +++ b/src/gallium/drivers/r600/r600_state_common.c @@ -249,7 +249,7 @@ static void r600_set_pipe_stencil_ref(struct pipe_context *ctx, const struct pipe_stencil_ref *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA]; + struct r600_dsa_state *dsa = (struct r600_dsa_state*)rctx->dsa_state.cso; struct r600_stencil_ref ref; rctx->stencil_ref.pipe_state = *state; @@ -270,15 +270,13 @@ static void r600_set_pipe_stencil_ref(struct pipe_context *ctx, static void r600_bind_dsa_state(struct pipe_context *ctx, void *state) { struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_dsa *dsa = state; - struct r600_pipe_state *rstate; + struct r600_dsa_state *dsa = state; struct r600_stencil_ref ref; if (state == NULL) return; - rstate = &dsa->rstate; - rctx->states[rstate->id] = rstate; - r600_context_pipe_state_set(rctx, rstate); + + r600_set_cso_state_with_cb(&rctx->dsa_state, dsa, &dsa->buffer); ref.ref_value[0] = rctx->stencil_ref.pipe_state.ref_value[0]; ref.ref_value[1] = rctx->stencil_ref.pipe_state.ref_value[1]; @@ -452,18 +450,12 @@ static void r600_delete_blend_state(struct pipe_context *ctx, void *state) FREE(blend); } -static void r600_delete_state(struct pipe_context *ctx, void *state) +static void r600_delete_dsa_state(struct pipe_context *ctx, void *state) { - struct r600_context *rctx = (struct r600_context *)ctx; - struct r600_pipe_state *rstate = (struct r600_pipe_state *)state; + struct r600_dsa_state *dsa = (struct r600_dsa_state *)state; - if (rctx->states[rstate->id] == rstate) { - rctx->states[rstate->id] = NULL; - } - for (int i = 0; i < rstate->nregs; i++) { - pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL); - } - free(rstate); + r600_release_command_buffer(&dsa->buffer); + free(dsa); } static void r600_bind_vertex_elements(struct pipe_context *ctx, void *state) @@ -1516,7 +1508,7 @@ void r600_init_common_state_functions(struct r600_context *rctx) rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler_states; rctx->context.bind_vs_state = r600_bind_vs_state; rctx->context.delete_blend_state = r600_delete_blend_state; - rctx->context.delete_depth_stencil_alpha_state = r600_delete_state; + rctx->context.delete_depth_stencil_alpha_state = r600_delete_dsa_state; rctx->context.delete_fs_state = r600_delete_ps_state; rctx->context.delete_rasterizer_state = r600_delete_rs_state; rctx->context.delete_sampler_state = r600_delete_sampler_state;