From: Cesar Strauss <cestrauss@gmail.com>
Date: Wed, 3 Jun 2020 01:07:33 +0000 (-0300)
Subject: Pass along the operand, in the cycle in which go is active
X-Git-Tag: div_pipeline~637^2~20
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef7438b05eee0a781e4fcfc09590bdb8f2c5e215;p=soc.git

Pass along the operand, in the cycle in which go is active
---

diff --git a/src/soc/experiment/test/test_compalu_multi.py b/src/soc/experiment/test/test_compalu_multi.py
index e80f2317..c92ceb42 100644
--- a/src/soc/experiment/test/test_compalu_multi.py
+++ b/src/soc/experiment/test/test_compalu_multi.py
@@ -139,7 +139,7 @@ class CompUnitParallelTest:
         self.imm = self.imm_ok = 0
         self.rdmaskn = (0, 0)
         # input data:
-        self.a = self.b = 0
+        self.operands = (0, 0)
 
     def driver(self):
         print("Begin parallel test.")
@@ -149,8 +149,7 @@ class CompUnitParallelTest:
     def operation(self, a, b, op, inv_a=0, imm=0, imm_ok=0, zero_a=0,
                   rdmaskn=(0, 0)):
         # store data for the operation
-        self.a = a
-        self.b = b
+        self.operands = (a, b)
         self.op = op
         self.inv_a = inv_a
         self.imm = imm
@@ -268,8 +267,9 @@ class CompUnitParallelTest:
         rel = yield self.dut.rd.rel[rd_idx]
         assert rel
 
-        # assert go for one cycle
+        # assert go for one cycle, passing along the operand value
         yield self.dut.rd.go[rd_idx].eq(1)
+        yield self.dut.src_i[rd_idx].eq(self.operands[rd_idx])
         yield
 
         # rel must keep high, since go was inactive in the last cycle
@@ -278,6 +278,7 @@ class CompUnitParallelTest:
 
         # finish the go one-clock pulse
         yield self.dut.rd.go[rd_idx].eq(0)
+        yield self.dut.src_i[rd_idx].eq(0)
         yield
 
         # rel must have gone low in response to go being high
@@ -285,9 +286,6 @@ class CompUnitParallelTest:
         rel = yield self.dut.rd.rel[rd_idx]
         assert not rel
 
-        # TODO: also when dut.rd.go is set, put the expected value into
-        # the src_i.  use dut.get_in[rd_idx] to do so
-
     def wr(self, wr_idx):
         # monitor self.dut.wr.req[rd_idx] and sets dut.wr.go[idx] for one cycle
         yield