From: Sebastien Bourdeauducq Date: Sat, 23 Feb 2013 18:42:29 +0000 (+0100) Subject: generic_platform/get_verilog: pass additional args to verilog.convert X-Git-Tag: 24jan2021_ls180~2099^2~443^2~64 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ef833422c77c83ee81018ceb7cec30914a733fd3;p=litex.git generic_platform/get_verilog: pass additional args to verilog.convert --- diff --git a/mibuild/generic_platform.py b/mibuild/generic_platform.py index 6777e765..ca5d9bd0 100644 --- a/mibuild/generic_platform.py +++ b/mibuild/generic_platform.py @@ -197,7 +197,7 @@ class GenericPlatform: if language is not None: self.add_source(os.path.join(root, filename), language) - def get_verilog(self, fragment, clock_domains=None): + def get_verilog(self, fragment, clock_domains=None, **kwargs): # We may create a temporary clock/reset generator that would request pins. # Save the constraint manager state so that such pin requests disappear # at the end of this function. @@ -214,7 +214,7 @@ class GenericPlatform: frag = fragment # generate Verilog src, vns = verilog.convert(frag, self.constraint_manager.get_io_signals(), - clock_domains=clock_domains, return_ns=True) + clock_domains=clock_domains, return_ns=True, **kwargs) # resolve signal names in constraints sc = self.constraint_manager.get_sig_constraints() named_sc = [(vns.get_name(sig), pins, others, resource) for sig, pins, others, resource in sc]