From: Jean-Paul Chaput Date: Fri, 7 Aug 2020 11:19:39 +0000 (+0200) Subject: Merge branch 'master' of ssh://libre-riscv.org:922/soclayout X-Git-Tag: partial-core-ls180-gdsii~91 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=efca2fa7a9211cecd6177c1220f9cdf50d0d38db;p=soclayout.git Merge branch 'master' of ssh://libre-riscv.org:922/soclayout Conflicts: experiments9/doDesign.py --- efca2fa7a9211cecd6177c1220f9cdf50d0d38db diff --cc experiments9/doDesign.py index 22e9707,f9ae7c9..8a89103 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@@ -438,38 -438,38 +438,38 @@@ def scriptMain ( **kw ) blockSpr0 = Block.create \ ( spr0 , ioPins=[ - (IN , 'coresync_clk' , l(805.0) ) - , (IW | AB, 'cu_issue_i' , 0, l(20), 1) - , (IW | AB, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1) - , (IW | AB, 'coresync_rst' , 0, l(20), 1) - , (IW | AB, 'src4_i' , 0, l(10), 1) - , (IW | AB, 'src5_i({})' , 0, l(10), 2) - , (IW | AB, 'src6_i({})' , 0, l(10), 2) - , (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 6) - , (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 6) - , (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 6) - , (IW | AB, 'oper_i_alu_spr0_insn_type({})', 0, l(20), 7) - , (IW | AB, 'oper_i_alu_spr0_fn_unit({})' , 0, l(20), 11) - , (IW | AB, 'oper_i_alu_spr0_insn({})' , 0, l(20), 32) - , (IW | AB, 'src3_i({})' , 0, l(10), 64) - , (IS | AB, 'src1_i({})' , 0, l(10), 64) - , (IS | AB, 'src2_i({})' , 0, l(5), 64) - , (IE | AE , 'cu_busy_o' , 0, l(20), 1) - , (IE | AE , 'dest4_o' , 0, l(20), 1) - , (IE | AE , 'fast1_ok' , 0, l(20), 1) - , (IE | AE , 'o_ok' , 0, l(20), 1) - , (IE | AE , 'spr1_ok' , 0, l(20), 1) - , (IE | AE , 'xer_ca_ok' , 0, l(20), 1) - , (IE | AE , 'xer_ov_ok' , 0, l(20), 1) - , (IE | AE , 'xer_so_ok' , 0, l(20), 1) - , (IE | AE , 'cu_rd_rel_o({})' , 0, 0, 6) - , (IE | AE , 'cu_wr_rel_o({})' , 0, 0, 6) - , (IE | AE , 'dest5_o({})' , 0, 0, 2) - , (IE | AE , 'dest6_o({})' , 0, 0, 2) - , (IE | AE , 'dest3_o({})' , 0, l(20), 64) - , (IS | AE , 'dest2_o({})' , 0, l(20), 64) - , (IS | AE , 'dest1_o({})' , 0, l(20), 64) - ] + (IN , 'coresync_clk' , l(805.0) ), + (IW | AB, 'cu_issue_i' , 0, l(20), 1), + (IW | AB, 'oper_i_alu_spr0_is_32bit' , 0, l(20), 1), + (IW | AB, 'coresync_rst' , 0, l(20), 1), + (IW | AB, 'src4_i' , 0, l(10), 1), + (IW | AB, 'src5_i({})' , 0, l(10), 2), + (IW | AB, 'src6_i({})' , 0, l(10), 2), + (IW | AB, 'cu_rd_go_i({})' , 0, l(20), 6), + (IW | AB, 'cu_rdmaskn_i({})' , 0, l(20), 6), + (IW | AB, 'cu_wr_go_i({})' , 0, l(20), 6), + (IW | AB, 'oper_i_alu_spr0_insn_type({})', 0, l(20), 7), + (IW | AB, 'oper_i_alu_spr0_fn_unit({})' , 0, l(20), 11), + (IW | AB, 'oper_i_alu_spr0_insn({})' , 0, l(20), 32), + (IW | AB, 'src3_i({})' , 0, l(10), 64), + (IS | AB, 'src1_i({})' , 0, l(10), 64), + (IS | AB, 'src2_i({})' , 0, l(5), 64), + (IE | AE, 'cu_busy_o' , 0, l(20), 1), + (IE | AE, 'dest4_o' , 0, l(20), 1), + (IE | AE, 'fast1_ok' , 0, l(20), 1), + (IE | AE, 'o_ok' , 0, l(20), 1), + (IE | AE, 'spr1_ok' , 0, l(20), 1), + (IE | AE, 'xer_ca_ok' , 0, l(20), 1), + (IE | AE, 'xer_ov_ok' , 0, l(20), 1), + (IE | AE, 'xer_so_ok' , 0, l(20), 1), + (IE | AE, 'cu_rd_rel_o({})' , 0, 0, 6), + (IE | AE, 'cu_wr_rel_o({})' , 0, 0, 6), - (IN | AE, 'dest5_o({})' , 0, 0, 2), - (IN | AE, 'dest6_o({})' , 0, 0, 2), ++ (IE | AE, 'dest5_o({})' , 0, 0, 2), ++ (IE | AE, 'dest6_o({})' , 0, 0, 2), + (IE | AE, 'dest3_o({})' , 0, l(20), 64), - (IE | AE, 'dest2_o({})' , 0, l(20), 64), - (IE | AE, 'dest1_o({})' , 0, l(20), 64), ++ (IS | AE, 'dest2_o({})' , 0, l(20), 64), ++ (IS | AE, 'dest1_o({})' , 0, l(20), 64), + ] ) blockSpr0.state.cfg.etesian.uniformDensity = True blockSpr0.state.cfg.etesian.spaceMargin = 0.5 @@@ -558,20 -557,21 +558,22 @@@ cellInt = af.getCell( 'int', CRL.Catalog.State.Views ) blockInt = Block.create \ ( cellInt - , ioPins=[ (IN , 'coresync_clk' , l(805.0) ) - , (IW | AB, 'coresync_rst' , 0, l(20), 1) - , (IN | AB, 'wen({})' , 0, l(20), 32) - , (IN | AB, 'wen_1({})' , 0, l(20), 32) - , (IN | AB, 'dmi_ren({})' , 0, l(20), 32) - , (IN | AB, 'src1_ren({})' , 0, l(20), 32) - , (IN | AB, 'src2_ren({})' , 0, l(20), 32) - , (IN | AB, 'src3_ren({})' , 0, l(20), 32) - , (IN | AB, 'data_i({})' , 0, l(20), 64) - , (IN | AB, 'data_i_2({})' , 0, l(20), 64) - , (IN | AE , 'dmi_data_o({})' , 0, l(10), 64) - , (IN | AE , 'src1_data_o({})' , 0, l(10), 64) - , (IN | AE , 'src2_data_o({})' , 0, l(10), 64) - , (IN | AE , 'src3_data_o({})' , 0, l(10), 64) - ] + , ioPins=[ + (IN , 'coresync_clk' , l(805.0) ), + (IW | AB, 'coresync_rst' , 0, l(20), 1), + (IW | AB, 'wen({})' , 0, l(20), 32), + (IW | AB, 'wen_1({})' , 0, l(20), 32), ++ (IN | AB, 'dmi_ren({})' , 0, l(20), 32), + (IW | AB, 'src1_ren({})' , 0, l(20), 32), + (IW | AB, 'src2_ren({})' , 0, l(20), 32), + (IW | AB, 'src3_ren({})' , 0, l(20), 32), + (IS | AB, 'data_i({})' , 0, l(20), 64), + (IS | AB, 'data_i_2({})' , 0, l(20), 64), ++ (IN | AE, 'dmi_data_o({})' , 0, l(10), 64), + (IN | AE, 'src1_data_o({})' , 0, l(10), 64), + (IN | AE, 'src2_data_o({})' , 0, l(10), 64), + (IN | AE, 'src3_data_o({})' , 0, l(10), 64), + ] ) blockInt.state.cfg.etesian.uniformDensity = True blockInt.state.cfg.etesian.aspectRatio = 1.0