From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 29 Sep 2018 11:16:00 +0000 (+0100)
Subject: fix bug in sv template where FRS2 was checking rs3
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=efd51d3fc576073cb8857e6e6d7b5ae5507c0b5b;p=riscv-isa-sim.git

fix bug in sv template where FRS2 was checking rs3
---

diff --git a/riscv/insn_template_sv.cc b/riscv/insn_template_sv.cc
index 83c9b44..9533e83 100644
--- a/riscv/insn_template_sv.cc
+++ b/riscv/insn_template_sv.cc
@@ -58,7 +58,7 @@ reg_t FN(processor_t* p, insn_t s_insn, reg_t pc)
 #ifdef USING_REG_FRS2
   insn.sv_check_reg(false, s_insn.rs2()) |
 #endif
-#ifdef USING_REG_FRS2
+#ifdef USING_REG_FRS3
   insn.sv_check_reg(false, s_insn.rs3()) |
 #endif
 #ifdef USING_REG_RVC_FRS2