From: Clifford Wolf Date: Sat, 19 Jul 2014 13:46:11 +0000 (+0200) Subject: Improved memory_share log messages X-Git-Tag: yosys-0.4~538 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=efd9604dfb92fda05c3efea67b7c32d812717fa8;p=yosys.git Improved memory_share log messages --- diff --git a/passes/memory/memory_share.cc b/passes/memory/memory_share.cc index cde5f2183..dc015f969 100644 --- a/passes/memory/memory_share.cc +++ b/passes/memory/memory_share.cc @@ -208,7 +208,7 @@ struct MemoryShareWorker if (async_rd_bits.empty()) return; - log("Populating enable bits on write ports of memory %s with aync read feedback:\n", log_id(memid)); + log("Populating enable bits on write ports of memory %s.%s with aync read feedback:\n", log_id(module), log_id(memid)); for (auto cell : wr_ports) { @@ -345,7 +345,7 @@ struct MemoryShareWorker if (wr_ports.size() <= 1) return; - log("Consolidating write ports of memory %s by address:\n", log_id(memid)); + log("Consolidating write ports of memory %s.%s by address:\n", log_id(module), log_id(memid)); std::map last_port_by_addr; std::vector> active_bits_on_port; @@ -501,7 +501,7 @@ struct MemoryShareWorker port_is_always_active:; } - log("Consolidating write ports of memory %s using sat-based resource sharing:\n", log_id(memid)); + log("Consolidating write ports of memory %s.%s using sat-based resource sharing:\n", log_id(module), log_id(memid)); bool cache_clk_enable = false; bool cache_clk_polarity = false;