From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 9 Dec 2019 22:20:35 +0000 (-0800)
Subject: unmap $__ICE40_CARRY_WRAPPER in test
X-Git-Tag: working-ls180~931^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=eff858cd33403a13736ac74cce6964648306e594;p=yosys.git

unmap $__ICE40_CARRY_WRAPPER in test
---

diff --git a/tests/arch/ice40/ice40_opt.ys b/tests/arch/ice40/ice40_opt.ys
index 860e2e211..5186d4800 100644
--- a/tests/arch/ice40/ice40_opt.ys
+++ b/tests/arch/ice40/ice40_opt.ys
@@ -1,3 +1,23 @@
+read_verilog -icells -formal <<EOT
+module \$__ICE40_CARRY_WRAPPER (output CO, O, input A, B, CI, I0, I3);
+  parameter LUT = 0;
+  SB_CARRY carry (
+    .I0(A),
+    .I1(B),
+    .CI(CI),
+    .CO(CO)
+  );
+  \$lut #(
+    .WIDTH(4),
+    .LUT(LUT)
+  ) lut (
+    .A({I0,A,B,I3}),
+    .Y(O)
+  );
+endmodule
+EOT
+design -stash unmap
+
 read_verilog -icells -formal <<EOT
 module top(input CI, I0, output [1:0] CO, output O);
     wire A = 1'b0, B = 1'b0;
@@ -20,7 +40,7 @@ module top(input CI, I0, output [1:0] CO, output O);
 endmodule
 EOT
 
-equiv_opt -assert -map +/ice40/cells_map.v -map +/ice40/cells_sim.v ice40_opt
+equiv_opt -assert -map %unmap -map +/ice40/cells_sim.v ice40_opt
 design -load postopt
 select -assert-count 1 t:*
 select -assert-count 1 t:$lut