From: whitequark <cz@m-labs.hk>
Date: Sun, 23 Dec 2018 09:20:02 +0000 (+0000)
Subject: back.rtlil: do not translate empty fragments.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=effc41f14003a86481f383d00a9009135f59156e;p=nmigen.git

back.rtlil: do not translate empty fragments.

The resulting Verilog confuses some frontends.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 817f9b2..d4a011c 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -627,6 +627,9 @@ def convert_fragment(builder, fragment, name, top):
         # name) names.
         memories = OrderedDict()
         for subfragment, sub_name in fragment.subfragments:
+            if not subfragment.ports:
+                continue
+
             sub_params = OrderedDict()
             if hasattr(subfragment, "parameters"):
                 for param_name, param_value in subfragment.parameters.items():