From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 28 Mar 2019 14:07:44 +0000 (+0000)
Subject: move flexible ports fn to MultiOutControlBase
X-Git-Tag: ls180-24jan2020~1431
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f00201d658112c173ddb935fb331d35c874a5628;p=ieee754fpu.git

move flexible ports fn to MultiOutControlBase
---

diff --git a/src/add/multipipe.py b/src/add/multipipe.py
index 0518cfeb..8abdc172 100644
--- a/src/add/multipipe.py
+++ b/src/add/multipipe.py
@@ -126,16 +126,22 @@ class MultiOutControlBase:
         return eq(self.p.i_data, i)
 
     def ports(self):
-        res = []
-        res += [self.p.i_valid, self.p.o_ready,
-                self.p.i_data] # XXX need flattening!
+        res = [self.p.i_valid, self.p.o_ready]
+        if hasattr(self.p.i_data, "ports"):
+            res += self.p.i_data.ports()
+        else:
+            res += self.p.i_data
+
         for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid,
-                    self.n[i].o_data]   # XXX need flattening!
+            n = self.n[i]
+            res += [n.i_ready, n.o_valid]
+            if hasattr(n.o_data, "ports"):
+                res += n.o_data.ports()
+            else:
+                res += n.o_data
         return res
 
 
-
 class CombMultiOutPipeline(MultiOutControlBase):
     """ A multi-input Combinatorial block conforming to the Pipeline API
 
@@ -275,8 +281,6 @@ class CombMuxOutPipe(CombMultiOutPipeline):
         # HACK: n-mux is also the stage... so set the muxid equal to input mid
         stage.m_id = self.p.i_data.mid
 
-    def ports(self):
-        return self.p_mux.ports()
 
 
 class InputPriorityArbiter:
diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index 54b69f83..62880a41 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -1897,14 +1897,6 @@ class FPADDMuxOutPipe(CombMuxOutPipe):
         stage = PassThroughStage(iospec)
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    self.n[i].o_data.ports()
-        return res
-
 
 class FPADDMuxInOut:
     """ Reservation-Station version of FPADD pipeline.
diff --git a/src/add/test_inout_mux_pipe.py b/src/add/test_inout_mux_pipe.py
index ada5e1cb..1bfc8dfe 100644
--- a/src/add/test_inout_mux_pipe.py
+++ b/src/add/test_inout_mux_pipe.py
@@ -198,14 +198,6 @@ class TestMuxOutPipe(CombMuxOutPipe):
         stage = PassThroughStage()
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    self.n[i].o_data.ports()
-        return res
-
 
 class TestInOutPipe:
     def __init__(self, num_rows=4):
diff --git a/src/add/test_outmux_pipe.py b/src/add/test_outmux_pipe.py
index 3e8a5559..67b03132 100644
--- a/src/add/test_outmux_pipe.py
+++ b/src/add/test_outmux_pipe.py
@@ -221,15 +221,6 @@ class TestPriorityMuxPipe(CombMuxOutPipe):
         stage = PassThroughStage()
         CombMuxOutPipe.__init__(self, stage, n_len=self.num_rows)
 
-    def ports(self):
-        res = [self.p.i_valid, self.p.o_ready] + \
-                self.p.i_data.ports()
-        for i in range(len(self.n)):
-            res += [self.n[i].i_ready, self.n[i].o_valid] + \
-                    [self.n[i].o_data]
-                    #self.n[i].o_data.ports()
-        return res
-
 
 class TestSyncToPriorityPipe:
     def __init__(self):