From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Fri, 21 Jan 2011 04:37:22 +0000 (-0800)
Subject: [sim, pk, xcc, opcodes] great instruction renaming of 2011
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0063c2e8b2ba6ec5e0147121e5ee2d9ee3ad2a4;p=riscv-isa-sim.git

[sim, pk, xcc, opcodes] great instruction renaming of 2011
---

diff --git a/riscv/execute.h b/riscv/execute.h
index b8e396a..88b5a84 100644
--- a/riscv/execute.h
+++ b/riscv/execute.h
@@ -98,18 +98,47 @@ switch((insn.bits >> 0x0) & 0x7f)
     }
     break;
   }
+  case 0x67:
+  {
+    switch((insn.bits >> 0x7) & 0x7)
+    {
+      case 0x0:
+      {
+        if((insn.bits & 0xfff) == 0x67)
+        {
+          #include "insns/fsel_s.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      case 0x3:
+      {
+        if((insn.bits & 0xfff) == 0x1e7)
+        {
+          #include "insns/fsel_d.h"
+          break;
+        }
+        #include "insns/unimp.h"
+      }
+      default:
+      {
+        #include "insns/unimp.h"
+      }
+    }
+    break;
+  }
   case 0x68:
   {
     switch((insn.bits >> 0x7) & 0x7)
     {
       case 0x2:
       {
-        #include "insns/l_s.h"
+        #include "insns/lf_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/l_d.h"
+        #include "insns/lf_d.h"
         break;
       }
       default:
@@ -125,12 +154,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x2:
       {
-        #include "insns/s_s.h"
+        #include "insns/sf_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/s_d.h"
+        #include "insns/sf_d.h"
         break;
       }
       default:
@@ -146,39 +175,39 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        if((insn.bits & 0x1ffff) == 0x1506a)
+        if((insn.bits & 0x1ffff) == 0x606a)
         {
-          #include "insns/c_eq_s.h"
+          #include "insns/fsinjn_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x506a)
+        if((insn.bits & 0x7c1ffff) == 0x1846a)
         {
-          #include "insns/sgninj_s.h"
+          #include "insns/mff_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xa06a)
+        if((insn.bits & 0x3ff1ff) == 0x1306a)
         {
-          #include "insns/cvt_w_s.h"
+          #include "insns/fcvt_s_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xe06a)
+        if((insn.bits & 0x1f1ff) == 0x6a)
         {
-          #include "insns/cvt_s_w.h"
+          #include "insns/fadd_s.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x6a)
+        if((insn.bits & 0x3ff1ff) == 0xe06a)
         {
-          #include "insns/add_s.h"
+          #include "insns/fcvt_s_w.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x906a)
+        if((insn.bits & 0x3ff1ff) == 0xb06a)
         {
-          #include "insns/cvtu_l_s.h"
+          #include "insns/fcvtu_w_s.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x1846a)
+        if((insn.bits & 0x3ff1ff) == 0x806a)
         {
-          #include "insns/mff_s.h"
+          #include "insns/fcvt_l_s.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x1c46a)
@@ -186,158 +215,153 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/mtf_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x606a)
+        if((insn.bits & 0x1f1ff) == 0x306a)
         {
-          #include "insns/sgninjn_s.h"
+          #include "insns/fdiv_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x806a)
+        if((insn.bits & 0x1ffff) == 0x1606a)
         {
-          #include "insns/cvt_l_s.h"
+          #include "insns/fc_lt_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xf06a)
+        if((insn.bits & 0x1f1ff) == 0x206a)
         {
-          #include "insns/cvtu_s_w.h"
+          #include "insns/fmul_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xd06a)
+        if((insn.bits & 0x1ffff) == 0x706a)
         {
-          #include "insns/cvtu_s_l.h"
+          #include "insns/fsmul_s.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x106a)
+        if((insn.bits & 0x3ff1ff) == 0xa06a)
         {
-          #include "insns/sub_s.h"
+          #include "insns/fcvt_w_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x406a)
+        if((insn.bits & 0x1ffff) == 0x506a)
         {
-          #include "insns/sqrt_s.h"
+          #include "insns/fsinj_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1606a)
+        if((insn.bits & 0x1f1ff) == 0x106a)
         {
-          #include "insns/c_lt_s.h"
+          #include "insns/fsub_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x706a)
+        if((insn.bits & 0x1ffff) == 0x1706a)
         {
-          #include "insns/sgnmul_s.h"
+          #include "insns/fc_le_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xc06a)
+        if((insn.bits & 0x3ff1ff) == 0xf06a)
         {
-          #include "insns/cvt_s_l.h"
+          #include "insns/fcvtu_s_w.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x306a)
+        if((insn.bits & 0x3ff1ff) == 0xd06a)
         {
-          #include "insns/div_s.h"
+          #include "insns/fcvtu_s_l.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x1306a)
+        if((insn.bits & 0x3ff1ff) == 0x906a)
         {
-          #include "insns/cvt_s_d.h"
+          #include "insns/fcvtu_l_s.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1706a)
+        if((insn.bits & 0x3ff1ff) == 0xc06a)
         {
-          #include "insns/c_le_s.h"
+          #include "insns/fcvt_s_l.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x206a)
+        if((insn.bits & 0x3ff1ff) == 0x406a)
         {
-          #include "insns/mul_s.h"
+          #include "insns/fsqrt_s.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb06a)
+        if((insn.bits & 0x1ffff) == 0x1506a)
         {
-          #include "insns/cvtu_w_s.h"
+          #include "insns/fc_eq_s.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x3:
       {
-        if((insn.bits & 0x3ff1ff) == 0xa1ea)
-        {
-          #include "insns/cvt_w_d.h"
-          break;
-        }
         if((insn.bits & 0x7c1ffff) == 0x185ea)
         {
           #include "insns/mff_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x51ea)
+        if((insn.bits & 0x1ffff) == 0x61ea)
         {
-          #include "insns/sgninj_d.h"
+          #include "insns/fsinjn_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x31ea)
+        if((insn.bits & 0x3ff1ff) == 0xc1ea)
         {
-          #include "insns/div_d.h"
+          #include "insns/fcvt_d_l.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x151ea)
+        if((insn.bits & 0x3fffff) == 0xe1ea)
         {
-          #include "insns/c_eq_d.h"
+          #include "insns/fcvt_d_w.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xd1ea)
+        if((insn.bits & 0x3fffff) == 0x101ea)
         {
-          #include "insns/cvtu_d_l.h"
+          #include "insns/fcvt_d_s.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xf1ea)
+        if((insn.bits & 0x7c1ffff) == 0x195ea)
         {
-          #include "insns/cvtu_d_w.h"
+          #include "insns/mffl_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x91ea)
+        if((insn.bits & 0x7c1ffff) == 0x1a5ea)
         {
-          #include "insns/cvtu_l_d.h"
+          #include "insns/mffh_d.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x195ea)
+        if((insn.bits & 0x3ff1ff) == 0x81ea)
         {
-          #include "insns/mffl_d.h"
+          #include "insns/fcvt_l_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x71ea)
+        if((insn.bits & 0x3fffff) == 0xf1ea)
         {
-          #include "insns/sgnmul_d.h"
+          #include "insns/fcvtu_d_w.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x1ea)
+        if((insn.bits & 0x1ffff) == 0x161ea)
         {
-          #include "insns/add_d.h"
+          #include "insns/fc_lt_d.h"
           break;
         }
-        if((insn.bits & 0x7c1ffff) == 0x1a5ea)
+        if((insn.bits & 0x1f1ff) == 0x21ea)
         {
-          #include "insns/mffh_d.h"
+          #include "insns/fmul_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x171ea)
+        if((insn.bits & 0x1ffff) == 0x151ea)
         {
-          #include "insns/c_le_d.h"
+          #include "insns/fc_eq_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x61ea)
+        if((insn.bits & 0x1ffff) == 0x71ea)
         {
-          #include "insns/sgninjn_d.h"
+          #include "insns/fsmul_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x81ea)
+        if((insn.bits & 0x1ffff) == 0x51ea)
         {
-          #include "insns/cvt_l_d.h"
+          #include "insns/fsinj_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x11ea)
+        if((insn.bits & 0x3ff1ff) == 0xa1ea)
         {
-          #include "insns/sub_d.h"
+          #include "insns/fcvt_w_d.h"
           break;
         }
         if((insn.bits & 0x3fffff) == 0x1c5ea)
@@ -345,39 +369,44 @@ switch((insn.bits >> 0x0) & 0x7f)
           #include "insns/mtf_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0x41ea)
+        if((insn.bits & 0x1ffff) == 0x171ea)
         {
-          #include "insns/sqrt_d.h"
+          #include "insns/fc_le_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0x101ea)
+        if((insn.bits & 0x3ff1ff) == 0xb1ea)
         {
-          #include "insns/cvt_d_s.h"
+          #include "insns/fcvtu_w_d.h"
           break;
         }
-        if((insn.bits & 0x3fffff) == 0xe1ea)
+        if((insn.bits & 0x1f1ff) == 0x1ea)
         {
-          #include "insns/cvt_d_w.h"
+          #include "insns/fadd_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xc1ea)
+        if((insn.bits & 0x3ff1ff) == 0x91ea)
         {
-          #include "insns/cvt_d_l.h"
+          #include "insns/fcvtu_l_d.h"
           break;
         }
-        if((insn.bits & 0x1f1ff) == 0x21ea)
+        if((insn.bits & 0x1f1ff) == 0x11ea)
         {
-          #include "insns/mul_d.h"
+          #include "insns/fsub_d.h"
           break;
         }
-        if((insn.bits & 0x3ff1ff) == 0xb1ea)
+        if((insn.bits & 0x3ff1ff) == 0x41ea)
         {
-          #include "insns/cvtu_w_d.h"
+          #include "insns/fsqrt_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x161ea)
+        if((insn.bits & 0x1f1ff) == 0x31ea)
+        {
+          #include "insns/fdiv_d.h"
+          break;
+        }
+        if((insn.bits & 0x3ff1ff) == 0xd1ea)
         {
-          #include "insns/c_lt_d.h"
+          #include "insns/fcvtu_d_l.h"
           break;
         }
         #include "insns/unimp.h"
@@ -452,12 +481,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/madd_s.h"
+        #include "insns/fmadd_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/madd_d.h"
+        #include "insns/fmadd_d.h"
         break;
       }
       default:
@@ -473,12 +502,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/msub_s.h"
+        #include "insns/fmsub_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/msub_d.h"
+        #include "insns/fmsub_d.h"
         break;
       }
       default:
@@ -494,12 +523,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/nmsub_s.h"
+        #include "insns/fnmsub_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/nmsub_d.h"
+        #include "insns/fnmsub_d.h"
         break;
       }
       default:
@@ -515,12 +544,12 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/nmadd_s.h"
+        #include "insns/fnmadd_s.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/nmadd_d.h"
+        #include "insns/fnmadd_d.h"
         break;
       }
       default:
@@ -817,37 +846,37 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/lb.h"
+        #include "insns/l_b.h"
         break;
       }
       case 0x1:
       {
-        #include "insns/lh.h"
+        #include "insns/l_h.h"
         break;
       }
       case 0x2:
       {
-        #include "insns/lw.h"
+        #include "insns/l_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/ld.h"
+        #include "insns/l_d.h"
         break;
       }
       case 0x4:
       {
-        #include "insns/lbu.h"
+        #include "insns/l_bu.h"
         break;
       }
       case 0x5:
       {
-        #include "insns/lhu.h"
+        #include "insns/l_hu.h"
         break;
       }
       case 0x6:
       {
-        #include "insns/lwu.h"
+        #include "insns/l_wu.h"
         break;
       }
       case 0x7:
@@ -872,22 +901,22 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x0:
       {
-        #include "insns/sb.h"
+        #include "insns/s_b.h"
         break;
       }
       case 0x1:
       {
-        #include "insns/sh.h"
+        #include "insns/s_h.h"
         break;
       }
       case 0x2:
       {
-        #include "insns/sw.h"
+        #include "insns/s_w.h"
         break;
       }
       case 0x3:
       {
-        #include "insns/sd.h"
+        #include "insns/s_d.h"
         break;
       }
       default:
@@ -903,88 +932,88 @@ switch((insn.bits >> 0x0) & 0x7f)
     {
       case 0x2:
       {
-        if((insn.bits & 0x1ffff) == 0x157a)
+        if((insn.bits & 0x1ffff) == 0x197a)
         {
-          #include "insns/amow_max.h"
+          #include "insns/amominu_w.h"
           break;
         }
         if((insn.bits & 0x1ffff) == 0x97a)
         {
-          #include "insns/amow_and.h"
+          #include "insns/amoand_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x117a)
+        if((insn.bits & 0x1ffff) == 0x1d7a)
         {
-          #include "insns/amow_min.h"
+          #include "insns/amomaxu_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0xd7a)
+        if((insn.bits & 0x1ffff) == 0x157a)
         {
-          #include "insns/amow_or.h"
+          #include "insns/amomax_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x197a)
+        if((insn.bits & 0x1ffff) == 0x17a)
         {
-          #include "insns/amow_minu.h"
+          #include "insns/amoadd_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x17a)
+        if((insn.bits & 0x1ffff) == 0xd7a)
         {
-          #include "insns/amow_add.h"
+          #include "insns/amoor_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x57a)
+        if((insn.bits & 0x1ffff) == 0x117a)
         {
-          #include "insns/amow_swap.h"
+          #include "insns/amomin_w.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1d7a)
+        if((insn.bits & 0x1ffff) == 0x57a)
         {
-          #include "insns/amow_maxu.h"
+          #include "insns/amoswap_w.h"
           break;
         }
         #include "insns/unimp.h"
       }
       case 0x3:
       {
-        if((insn.bits & 0x1ffff) == 0x1fa)
+        if((insn.bits & 0x1ffff) == 0x19fa)
         {
-          #include "insns/amo_add.h"
+          #include "insns/amominu_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x5fa)
+        if((insn.bits & 0x1ffff) == 0x9fa)
         {
-          #include "insns/amo_swap.h"
+          #include "insns/amoand_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0xdfa)
+        if((insn.bits & 0x1ffff) == 0x1dfa)
         {
-          #include "insns/amo_or.h"
+          #include "insns/amomaxu_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x15fa)
+        if((insn.bits & 0x1ffff) == 0x11fa)
         {
-          #include "insns/amo_max.h"
+          #include "insns/amomin_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x11fa)
+        if((insn.bits & 0x1ffff) == 0x1fa)
         {
-          #include "insns/amo_min.h"
+          #include "insns/amoadd_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x19fa)
+        if((insn.bits & 0x1ffff) == 0x15fa)
         {
-          #include "insns/amo_minu.h"
+          #include "insns/amomax_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x9fa)
+        if((insn.bits & 0x1ffff) == 0xdfa)
         {
-          #include "insns/amo_and.h"
+          #include "insns/amoor_d.h"
           break;
         }
-        if((insn.bits & 0x1ffff) == 0x1dfa)
+        if((insn.bits & 0x1ffff) == 0x5fa)
         {
-          #include "insns/amo_maxu.h"
+          #include "insns/amoswap_d.h"
           break;
         }
         #include "insns/unimp.h"
diff --git a/riscv/insns/add_d.h b/riscv/insns/add_d.h
deleted file mode 100644
index 48c76a7..0000000
--- a/riscv/insns/add_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_add(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/add_s.h b/riscv/insns/add_s.h
deleted file mode 100644
index 2fd5429..0000000
--- a/riscv/insns/add_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_add(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/amo_add.h b/riscv/insns/amo_add.h
deleted file mode 100644
index b8450bf..0000000
--- a/riscv/insns/amo_add.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2 + v);
-RD = v;
diff --git a/riscv/insns/amo_and.h b/riscv/insns/amo_and.h
deleted file mode 100644
index 586eb7f..0000000
--- a/riscv/insns/amo_and.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2 & v);
-RD = v;
diff --git a/riscv/insns/amo_max.h b/riscv/insns/amo_max.h
deleted file mode 100644
index 1a0bc8a..0000000
--- a/riscv/insns/amo_max.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-sreg_t v = mmu.load_int64(RS1);
-mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
-RD = v;
diff --git a/riscv/insns/amo_maxu.h b/riscv/insns/amo_maxu.h
deleted file mode 100644
index ccfaf1d..0000000
--- a/riscv/insns/amo_maxu.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, std::max(RS2,v));
-RD = v;
diff --git a/riscv/insns/amo_min.h b/riscv/insns/amo_min.h
deleted file mode 100644
index 4f3b6d6..0000000
--- a/riscv/insns/amo_min.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-sreg_t v = mmu.load_int64(RS1);
-mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
-RD = v;
diff --git a/riscv/insns/amo_minu.h b/riscv/insns/amo_minu.h
deleted file mode 100644
index c09c51a..0000000
--- a/riscv/insns/amo_minu.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, std::min(RS2,v));
-RD = v;
diff --git a/riscv/insns/amo_or.h b/riscv/insns/amo_or.h
deleted file mode 100644
index 76a4508..0000000
--- a/riscv/insns/amo_or.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2 | v);
-RD = v;
diff --git a/riscv/insns/amo_swap.h b/riscv/insns/amo_swap.h
deleted file mode 100644
index 43e3538..0000000
--- a/riscv/insns/amo_swap.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_xpr64;
-reg_t v = mmu.load_uint64(RS1);
-mmu.store_uint64(RS1, RS2);
-RD = v;
diff --git a/riscv/insns/amoadd_d.h b/riscv/insns/amoadd_d.h
new file mode 100644
index 0000000..b8450bf
--- /dev/null
+++ b/riscv/insns/amoadd_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 + v);
+RD = v;
diff --git a/riscv/insns/amoadd_w.h b/riscv/insns/amoadd_w.h
new file mode 100644
index 0000000..033b3c8
--- /dev/null
+++ b/riscv/insns/amoadd_w.h
@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 + v);
+RD = v;
diff --git a/riscv/insns/amoand_d.h b/riscv/insns/amoand_d.h
new file mode 100644
index 0000000..586eb7f
--- /dev/null
+++ b/riscv/insns/amoand_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 & v);
+RD = v;
diff --git a/riscv/insns/amoand_w.h b/riscv/insns/amoand_w.h
new file mode 100644
index 0000000..18a9249
--- /dev/null
+++ b/riscv/insns/amoand_w.h
@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 & v);
+RD = v;
diff --git a/riscv/insns/amomax_d.h b/riscv/insns/amomax_d.h
new file mode 100644
index 0000000..1a0bc8a
--- /dev/null
+++ b/riscv/insns/amomax_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::max(sreg_t(RS2),v));
+RD = v;
diff --git a/riscv/insns/amomax_w.h b/riscv/insns/amomax_w.h
new file mode 100644
index 0000000..ff9c2da
--- /dev/null
+++ b/riscv/insns/amomax_w.h
@@ -0,0 +1,3 @@
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
+RD = v;
diff --git a/riscv/insns/amomaxu_d.h b/riscv/insns/amomaxu_d.h
new file mode 100644
index 0000000..ccfaf1d
--- /dev/null
+++ b/riscv/insns/amomaxu_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::max(RS2,v));
+RD = v;
diff --git a/riscv/insns/amomaxu_w.h b/riscv/insns/amomaxu_w.h
new file mode 100644
index 0000000..f7b0b7f
--- /dev/null
+++ b/riscv/insns/amomaxu_w.h
@@ -0,0 +1,3 @@
+uint32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
+RD = v;
diff --git a/riscv/insns/amomin_d.h b/riscv/insns/amomin_d.h
new file mode 100644
index 0000000..4f3b6d6
--- /dev/null
+++ b/riscv/insns/amomin_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+sreg_t v = mmu.load_int64(RS1);
+mmu.store_uint64(RS1, std::min(sreg_t(RS2),v));
+RD = v;
diff --git a/riscv/insns/amomin_w.h b/riscv/insns/amomin_w.h
new file mode 100644
index 0000000..529ad50
--- /dev/null
+++ b/riscv/insns/amomin_w.h
@@ -0,0 +1,3 @@
+int32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
+RD = v;
diff --git a/riscv/insns/amominu_d.h b/riscv/insns/amominu_d.h
new file mode 100644
index 0000000..c09c51a
--- /dev/null
+++ b/riscv/insns/amominu_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, std::min(RS2,v));
+RD = v;
diff --git a/riscv/insns/amominu_w.h b/riscv/insns/amominu_w.h
new file mode 100644
index 0000000..2e9fd17
--- /dev/null
+++ b/riscv/insns/amominu_w.h
@@ -0,0 +1,3 @@
+uint32_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
+RD = v;
diff --git a/riscv/insns/amoor_d.h b/riscv/insns/amoor_d.h
new file mode 100644
index 0000000..76a4508
--- /dev/null
+++ b/riscv/insns/amoor_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2 | v);
+RD = v;
diff --git a/riscv/insns/amoor_w.h b/riscv/insns/amoor_w.h
new file mode 100644
index 0000000..741fbef
--- /dev/null
+++ b/riscv/insns/amoor_w.h
@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2 | v);
+RD = v;
diff --git a/riscv/insns/amoswap_d.h b/riscv/insns/amoswap_d.h
new file mode 100644
index 0000000..43e3538
--- /dev/null
+++ b/riscv/insns/amoswap_d.h
@@ -0,0 +1,4 @@
+require_xpr64;
+reg_t v = mmu.load_uint64(RS1);
+mmu.store_uint64(RS1, RS2);
+RD = v;
diff --git a/riscv/insns/amoswap_w.h b/riscv/insns/amoswap_w.h
new file mode 100644
index 0000000..30e6102
--- /dev/null
+++ b/riscv/insns/amoswap_w.h
@@ -0,0 +1,3 @@
+reg_t v = mmu.load_int32(RS1);
+mmu.store_uint32(RS1, RS2);
+RD = v;
diff --git a/riscv/insns/amow_add.h b/riscv/insns/amow_add.h
deleted file mode 100644
index 033b3c8..0000000
--- a/riscv/insns/amow_add.h
+++ /dev/null
@@ -1,3 +0,0 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 + v);
-RD = v;
diff --git a/riscv/insns/amow_and.h b/riscv/insns/amow_and.h
deleted file mode 100644
index 18a9249..0000000
--- a/riscv/insns/amow_and.h
+++ /dev/null
@@ -1,3 +0,0 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 & v);
-RD = v;
diff --git a/riscv/insns/amow_max.h b/riscv/insns/amow_max.h
deleted file mode 100644
index ff9c2da..0000000
--- a/riscv/insns/amow_max.h
+++ /dev/null
@@ -1,3 +0,0 @@
-int32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::max(int32_t(RS2),v));
-RD = v;
diff --git a/riscv/insns/amow_maxu.h b/riscv/insns/amow_maxu.h
deleted file mode 100644
index f7b0b7f..0000000
--- a/riscv/insns/amow_maxu.h
+++ /dev/null
@@ -1,3 +0,0 @@
-uint32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::max(uint32_t(RS2),v));
-RD = v;
diff --git a/riscv/insns/amow_min.h b/riscv/insns/amow_min.h
deleted file mode 100644
index 529ad50..0000000
--- a/riscv/insns/amow_min.h
+++ /dev/null
@@ -1,3 +0,0 @@
-int32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::min(int32_t(RS2),v));
-RD = v;
diff --git a/riscv/insns/amow_minu.h b/riscv/insns/amow_minu.h
deleted file mode 100644
index 2e9fd17..0000000
--- a/riscv/insns/amow_minu.h
+++ /dev/null
@@ -1,3 +0,0 @@
-uint32_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, std::min(uint32_t(RS2),v));
-RD = v;
diff --git a/riscv/insns/amow_or.h b/riscv/insns/amow_or.h
deleted file mode 100644
index 741fbef..0000000
--- a/riscv/insns/amow_or.h
+++ /dev/null
@@ -1,3 +0,0 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2 | v);
-RD = v;
diff --git a/riscv/insns/amow_swap.h b/riscv/insns/amow_swap.h
deleted file mode 100644
index 30e6102..0000000
--- a/riscv/insns/amow_swap.h
+++ /dev/null
@@ -1,3 +0,0 @@
-reg_t v = mmu.load_int32(RS1);
-mmu.store_uint32(RS1, RS2);
-RD = v;
diff --git a/riscv/insns/c_eq_d.h b/riscv/insns/c_eq_d.h
deleted file mode 100644
index 9db8760..0000000
--- a/riscv/insns/c_eq_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f64_eq(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/c_eq_s.h b/riscv/insns/c_eq_s.h
deleted file mode 100644
index 658e8f6..0000000
--- a/riscv/insns/c_eq_s.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f32_eq(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/c_le_d.h b/riscv/insns/c_le_d.h
deleted file mode 100644
index da76187..0000000
--- a/riscv/insns/c_le_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f64_le(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/c_le_s.h b/riscv/insns/c_le_s.h
deleted file mode 100644
index 9c83a17..0000000
--- a/riscv/insns/c_le_s.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f32_le(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/c_lt_d.h b/riscv/insns/c_lt_d.h
deleted file mode 100644
index 01d135a..0000000
--- a/riscv/insns/c_lt_d.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f64_lt(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/c_lt_s.h b/riscv/insns/c_lt_s.h
deleted file mode 100644
index 52eee5d..0000000
--- a/riscv/insns/c_lt_s.h
+++ /dev/null
@@ -1,3 +0,0 @@
-require_fp;
-RD = f32_lt(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_l.h b/riscv/insns/cvt_d_l.h
deleted file mode 100644
index 68c0482..0000000
--- a/riscv/insns/cvt_d_l.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_s.h b/riscv/insns/cvt_d_s.h
deleted file mode 100644
index 6b1a09c..0000000
--- a/riscv/insns/cvt_d_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_to_f64(FRS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_d_w.h b/riscv/insns/cvt_d_w.h
deleted file mode 100644
index 638a5ec..0000000
--- a/riscv/insns/cvt_d_w.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i32_to_f64(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_l_d.h b/riscv/insns/cvt_l_d.h
deleted file mode 100644
index bd460d5..0000000
--- a/riscv/insns/cvt_l_d.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_l_s.h b/riscv/insns/cvt_l_s.h
deleted file mode 100644
index 1ed4594..0000000
--- a/riscv/insns/cvt_l_s.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_d.h b/riscv/insns/cvt_s_d.h
deleted file mode 100644
index e5289c4..0000000
--- a/riscv/insns/cvt_s_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_to_f32(FRS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_l.h b/riscv/insns/cvt_s_l.h
deleted file mode 100644
index f149229..0000000
--- a/riscv/insns/cvt_s_l.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_s_w.h b/riscv/insns/cvt_s_w.h
deleted file mode 100644
index 12b1e73..0000000
--- a/riscv/insns/cvt_s_w.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i32_to_f32(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_w_d.h b/riscv/insns/cvt_w_d.h
deleted file mode 100644
index e924467..0000000
--- a/riscv/insns/cvt_w_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i32_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvt_w_s.h b/riscv/insns/cvt_w_s.h
deleted file mode 100644
index 809797f..0000000
--- a/riscv/insns/cvt_w_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i32_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_d_l.h b/riscv/insns/cvtu_d_l.h
deleted file mode 100644
index 68c0482..0000000
--- a/riscv/insns/cvtu_d_l.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f64(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_d_w.h b/riscv/insns/cvtu_d_w.h
deleted file mode 100644
index 2757790..0000000
--- a/riscv/insns/cvtu_d_w.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = ui32_to_f64(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_l_d.h b/riscv/insns/cvtu_l_d.h
deleted file mode 100644
index bd460d5..0000000
--- a/riscv/insns/cvtu_l_d.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_l_s.h b/riscv/insns/cvtu_l_s.h
deleted file mode 100644
index 1ed4594..0000000
--- a/riscv/insns/cvtu_l_s.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_i64_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_s_l.h b/riscv/insns/cvtu_s_l.h
deleted file mode 100644
index f149229..0000000
--- a/riscv/insns/cvtu_s_l.h
+++ /dev/null
@@ -1,5 +0,0 @@
-require_xpr64;
-require_fp;
-softfloat_roundingMode = RM;
-FRD = i64_to_f32(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_s_w.h b/riscv/insns/cvtu_s_w.h
deleted file mode 100644
index 4c53c01..0000000
--- a/riscv/insns/cvtu_s_w.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = ui32_to_f32(RS1);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_w_d.h b/riscv/insns/cvtu_w_d.h
deleted file mode 100644
index 93860e8..0000000
--- a/riscv/insns/cvtu_w_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f64_to_ui32_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/cvtu_w_s.h b/riscv/insns/cvtu_w_s.h
deleted file mode 100644
index 04b8fb2..0000000
--- a/riscv/insns/cvtu_w_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-RD = f32_to_ui32_r_minMag(FRS1,true);
-set_fp_exceptions;
diff --git a/riscv/insns/div_d.h b/riscv/insns/div_d.h
deleted file mode 100644
index aa00c98..0000000
--- a/riscv/insns/div_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_div(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/div_s.h b/riscv/insns/div_s.h
deleted file mode 100644
index 8c76587..0000000
--- a/riscv/insns/div_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_div(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/fadd_d.h b/riscv/insns/fadd_d.h
new file mode 100644
index 0000000..48c76a7
--- /dev/null
+++ b/riscv/insns/fadd_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_add(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fadd_s.h b/riscv/insns/fadd_s.h
new file mode 100644
index 0000000..2fd5429
--- /dev/null
+++ b/riscv/insns/fadd_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_add(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fc_eq_d.h b/riscv/insns/fc_eq_d.h
new file mode 100644
index 0000000..9db8760
--- /dev/null
+++ b/riscv/insns/fc_eq_d.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f64_eq(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fc_eq_s.h b/riscv/insns/fc_eq_s.h
new file mode 100644
index 0000000..658e8f6
--- /dev/null
+++ b/riscv/insns/fc_eq_s.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f32_eq(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fc_le_d.h b/riscv/insns/fc_le_d.h
new file mode 100644
index 0000000..da76187
--- /dev/null
+++ b/riscv/insns/fc_le_d.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f64_le(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fc_le_s.h b/riscv/insns/fc_le_s.h
new file mode 100644
index 0000000..9c83a17
--- /dev/null
+++ b/riscv/insns/fc_le_s.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f32_le(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fc_lt_d.h b/riscv/insns/fc_lt_d.h
new file mode 100644
index 0000000..01d135a
--- /dev/null
+++ b/riscv/insns/fc_lt_d.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f64_lt(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fc_lt_s.h b/riscv/insns/fc_lt_s.h
new file mode 100644
index 0000000..52eee5d
--- /dev/null
+++ b/riscv/insns/fc_lt_s.h
@@ -0,0 +1,3 @@
+require_fp;
+RD = f32_lt(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_l.h b/riscv/insns/fcvt_d_l.h
new file mode 100644
index 0000000..68c0482
--- /dev/null
+++ b/riscv/insns/fcvt_d_l.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i64_to_f64(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_s.h b/riscv/insns/fcvt_d_s.h
new file mode 100644
index 0000000..6b1a09c
--- /dev/null
+++ b/riscv/insns/fcvt_d_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_to_f64(FRS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_d_w.h b/riscv/insns/fcvt_d_w.h
new file mode 100644
index 0000000..638a5ec
--- /dev/null
+++ b/riscv/insns/fcvt_d_w.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i32_to_f64(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_d.h b/riscv/insns/fcvt_l_d.h
new file mode 100644
index 0000000..bd460d5
--- /dev/null
+++ b/riscv/insns/fcvt_l_d.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_l_s.h b/riscv/insns/fcvt_l_s.h
new file mode 100644
index 0000000..1ed4594
--- /dev/null
+++ b/riscv/insns/fcvt_l_s.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_d.h b/riscv/insns/fcvt_s_d.h
new file mode 100644
index 0000000..e5289c4
--- /dev/null
+++ b/riscv/insns/fcvt_s_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_to_f32(FRS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_l.h b/riscv/insns/fcvt_s_l.h
new file mode 100644
index 0000000..f149229
--- /dev/null
+++ b/riscv/insns/fcvt_s_l.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i64_to_f32(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_s_w.h b/riscv/insns/fcvt_s_w.h
new file mode 100644
index 0000000..12b1e73
--- /dev/null
+++ b/riscv/insns/fcvt_s_w.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i32_to_f32(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_d.h b/riscv/insns/fcvt_w_d.h
new file mode 100644
index 0000000..e924467
--- /dev/null
+++ b/riscv/insns/fcvt_w_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i32_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvt_w_s.h b/riscv/insns/fcvt_w_s.h
new file mode 100644
index 0000000..809797f
--- /dev/null
+++ b/riscv/insns/fcvt_w_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i32_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_d_l.h b/riscv/insns/fcvtu_d_l.h
new file mode 100644
index 0000000..68c0482
--- /dev/null
+++ b/riscv/insns/fcvtu_d_l.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i64_to_f64(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_d_w.h b/riscv/insns/fcvtu_d_w.h
new file mode 100644
index 0000000..2757790
--- /dev/null
+++ b/riscv/insns/fcvtu_d_w.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = ui32_to_f64(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_l_d.h b/riscv/insns/fcvtu_l_d.h
new file mode 100644
index 0000000..bd460d5
--- /dev/null
+++ b/riscv/insns/fcvtu_l_d.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_l_s.h b/riscv/insns/fcvtu_l_s.h
new file mode 100644
index 0000000..1ed4594
--- /dev/null
+++ b/riscv/insns/fcvtu_l_s.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_i64_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_s_l.h b/riscv/insns/fcvtu_s_l.h
new file mode 100644
index 0000000..f149229
--- /dev/null
+++ b/riscv/insns/fcvtu_s_l.h
@@ -0,0 +1,5 @@
+require_xpr64;
+require_fp;
+softfloat_roundingMode = RM;
+FRD = i64_to_f32(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_s_w.h b/riscv/insns/fcvtu_s_w.h
new file mode 100644
index 0000000..4c53c01
--- /dev/null
+++ b/riscv/insns/fcvtu_s_w.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = ui32_to_f32(RS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_w_d.h b/riscv/insns/fcvtu_w_d.h
new file mode 100644
index 0000000..93860e8
--- /dev/null
+++ b/riscv/insns/fcvtu_w_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f64_to_ui32_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fcvtu_w_s.h b/riscv/insns/fcvtu_w_s.h
new file mode 100644
index 0000000..04b8fb2
--- /dev/null
+++ b/riscv/insns/fcvtu_w_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+RD = f32_to_ui32_r_minMag(FRS1,true);
+set_fp_exceptions;
diff --git a/riscv/insns/fdiv_d.h b/riscv/insns/fdiv_d.h
new file mode 100644
index 0000000..aa00c98
--- /dev/null
+++ b/riscv/insns/fdiv_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_div(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fdiv_s.h b/riscv/insns/fdiv_s.h
new file mode 100644
index 0000000..8c76587
--- /dev/null
+++ b/riscv/insns/fdiv_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_div(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fmadd_d.h b/riscv/insns/fmadd_d.h
new file mode 100644
index 0000000..f67853e
--- /dev/null
+++ b/riscv/insns/fmadd_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3);
+set_fp_exceptions;
diff --git a/riscv/insns/fmadd_s.h b/riscv/insns/fmadd_s.h
new file mode 100644
index 0000000..19db642
--- /dev/null
+++ b/riscv/insns/fmadd_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3);
+set_fp_exceptions;
diff --git a/riscv/insns/fmsub_d.h b/riscv/insns/fmsub_d.h
new file mode 100644
index 0000000..b1e9340
--- /dev/null
+++ b/riscv/insns/fmsub_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
+set_fp_exceptions;
diff --git a/riscv/insns/fmsub_s.h b/riscv/insns/fmsub_s.h
new file mode 100644
index 0000000..d3349f5
--- /dev/null
+++ b/riscv/insns/fmsub_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
+set_fp_exceptions;
diff --git a/riscv/insns/fmul_d.h b/riscv/insns/fmul_d.h
new file mode 100644
index 0000000..a8adedd
--- /dev/null
+++ b/riscv/insns/fmul_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_mul(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fmul_s.h b/riscv/insns/fmul_s.h
new file mode 100644
index 0000000..6475578
--- /dev/null
+++ b/riscv/insns/fmul_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_mul(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_d.h b/riscv/insns/fnmadd_d.h
new file mode 100644
index 0000000..1e2ee27
--- /dev/null
+++ b/riscv/insns/fnmadd_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
+set_fp_exceptions;
diff --git a/riscv/insns/fnmadd_s.h b/riscv/insns/fnmadd_s.h
new file mode 100644
index 0000000..78abb78
--- /dev/null
+++ b/riscv/insns/fnmadd_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
+set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_d.h b/riscv/insns/fnmsub_d.h
new file mode 100644
index 0000000..ae643a5
--- /dev/null
+++ b/riscv/insns/fnmsub_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
+set_fp_exceptions;
diff --git a/riscv/insns/fnmsub_s.h b/riscv/insns/fnmsub_s.h
new file mode 100644
index 0000000..cbb70ba
--- /dev/null
+++ b/riscv/insns/fnmsub_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
+set_fp_exceptions;
diff --git a/riscv/insns/fsel_d.h b/riscv/insns/fsel_d.h
new file mode 100644
index 0000000..fe74bcd
--- /dev/null
+++ b/riscv/insns/fsel_d.h
@@ -0,0 +1,3 @@
+require_fp;
+FRD = !f64_eq(FRS1, 0) ? FRS2 : FRS3;
+set_fp_exceptions;
diff --git a/riscv/insns/fsel_s.h b/riscv/insns/fsel_s.h
new file mode 100644
index 0000000..78b8f5d
--- /dev/null
+++ b/riscv/insns/fsel_s.h
@@ -0,0 +1,3 @@
+require_fp;
+FRD = !f32_eq(FRS1, 0) ? FRS2 : FRS3;
+set_fp_exceptions;
diff --git a/riscv/insns/fsinj_d.h b/riscv/insns/fsinj_d.h
new file mode 100644
index 0000000..f66e804
--- /dev/null
+++ b/riscv/insns/fsinj_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
diff --git a/riscv/insns/fsinj_s.h b/riscv/insns/fsinj_s.h
new file mode 100644
index 0000000..35609ac
--- /dev/null
+++ b/riscv/insns/fsinj_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsinjn_d.h b/riscv/insns/fsinjn_d.h
new file mode 100644
index 0000000..22de215
--- /dev/null
+++ b/riscv/insns/fsinjn_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
diff --git a/riscv/insns/fsinjn_s.h b/riscv/insns/fsinjn_s.h
new file mode 100644
index 0000000..dd66d71
--- /dev/null
+++ b/riscv/insns/fsinjn_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsmul_d.h b/riscv/insns/fsmul_d.h
new file mode 100644
index 0000000..331b6e4
--- /dev/null
+++ b/riscv/insns/fsmul_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = FRS1 ^ (FRS2 & INT64_MIN);
diff --git a/riscv/insns/fsmul_s.h b/riscv/insns/fsmul_s.h
new file mode 100644
index 0000000..b455406
--- /dev/null
+++ b/riscv/insns/fsmul_s.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/fsqrt_d.h b/riscv/insns/fsqrt_d.h
new file mode 100644
index 0000000..7647c9c
--- /dev/null
+++ b/riscv/insns/fsqrt_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_sqrt(FRS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fsqrt_s.h b/riscv/insns/fsqrt_s.h
new file mode 100644
index 0000000..426f241
--- /dev/null
+++ b/riscv/insns/fsqrt_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_sqrt(FRS1);
+set_fp_exceptions;
diff --git a/riscv/insns/fsub_d.h b/riscv/insns/fsub_d.h
new file mode 100644
index 0000000..e25eebb
--- /dev/null
+++ b/riscv/insns/fsub_d.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f64_sub(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/fsub_s.h b/riscv/insns/fsub_s.h
new file mode 100644
index 0000000..6c64d04
--- /dev/null
+++ b/riscv/insns/fsub_s.h
@@ -0,0 +1,4 @@
+require_fp;
+softfloat_roundingMode = RM;
+FRD = f32_sub(FRS1, FRS2);
+set_fp_exceptions;
diff --git a/riscv/insns/l_b.h b/riscv/insns/l_b.h
new file mode 100644
index 0000000..81ba7de
--- /dev/null
+++ b/riscv/insns/l_b.h
@@ -0,0 +1 @@
+RD = mmu.load_int8(RS1+SIMM);
diff --git a/riscv/insns/l_bu.h b/riscv/insns/l_bu.h
new file mode 100644
index 0000000..12c688a
--- /dev/null
+++ b/riscv/insns/l_bu.h
@@ -0,0 +1 @@
+RD = mmu.load_uint8(RS1+SIMM);
diff --git a/riscv/insns/l_d.h b/riscv/insns/l_d.h
index 123dea4..940d348 100644
--- a/riscv/insns/l_d.h
+++ b/riscv/insns/l_d.h
@@ -1,2 +1,2 @@
-require_fp;
-FRD = mmu.load_int64(RS1+SIMM);
+require_xpr64;
+RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/l_h.h b/riscv/insns/l_h.h
new file mode 100644
index 0000000..ec25bc4
--- /dev/null
+++ b/riscv/insns/l_h.h
@@ -0,0 +1 @@
+RD = mmu.load_int16(RS1+SIMM);
diff --git a/riscv/insns/l_hu.h b/riscv/insns/l_hu.h
new file mode 100644
index 0000000..0999c00
--- /dev/null
+++ b/riscv/insns/l_hu.h
@@ -0,0 +1 @@
+RD = mmu.load_uint16(RS1+SIMM);
diff --git a/riscv/insns/l_s.h b/riscv/insns/l_s.h
deleted file mode 100644
index 335fd7d..0000000
--- a/riscv/insns/l_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/l_w.h b/riscv/insns/l_w.h
new file mode 100644
index 0000000..769c9fd
--- /dev/null
+++ b/riscv/insns/l_w.h
@@ -0,0 +1 @@
+RD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/l_wu.h b/riscv/insns/l_wu.h
new file mode 100644
index 0000000..5e62b0f
--- /dev/null
+++ b/riscv/insns/l_wu.h
@@ -0,0 +1 @@
+RD = mmu.load_uint32(RS1+SIMM);
diff --git a/riscv/insns/lb.h b/riscv/insns/lb.h
deleted file mode 100644
index 81ba7de..0000000
--- a/riscv/insns/lb.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_int8(RS1+SIMM);
diff --git a/riscv/insns/lbu.h b/riscv/insns/lbu.h
deleted file mode 100644
index 12c688a..0000000
--- a/riscv/insns/lbu.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_uint8(RS1+SIMM);
diff --git a/riscv/insns/ld.h b/riscv/insns/ld.h
deleted file mode 100644
index 940d348..0000000
--- a/riscv/insns/ld.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_xpr64;
-RD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lf_d.h b/riscv/insns/lf_d.h
new file mode 100644
index 0000000..123dea4
--- /dev/null
+++ b/riscv/insns/lf_d.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = mmu.load_int64(RS1+SIMM);
diff --git a/riscv/insns/lf_w.h b/riscv/insns/lf_w.h
new file mode 100644
index 0000000..335fd7d
--- /dev/null
+++ b/riscv/insns/lf_w.h
@@ -0,0 +1,2 @@
+require_fp;
+FRD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/lh.h b/riscv/insns/lh.h
deleted file mode 100644
index ec25bc4..0000000
--- a/riscv/insns/lh.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_int16(RS1+SIMM);
diff --git a/riscv/insns/lhu.h b/riscv/insns/lhu.h
deleted file mode 100644
index 0999c00..0000000
--- a/riscv/insns/lhu.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_uint16(RS1+SIMM);
diff --git a/riscv/insns/lw.h b/riscv/insns/lw.h
deleted file mode 100644
index 769c9fd..0000000
--- a/riscv/insns/lw.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_int32(RS1+SIMM);
diff --git a/riscv/insns/lwu.h b/riscv/insns/lwu.h
deleted file mode 100644
index 5e62b0f..0000000
--- a/riscv/insns/lwu.h
+++ /dev/null
@@ -1 +0,0 @@
-RD = mmu.load_uint32(RS1+SIMM);
diff --git a/riscv/insns/madd_d.h b/riscv/insns/madd_d.h
deleted file mode 100644
index f67853e..0000000
--- a/riscv/insns/madd_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3);
-set_fp_exceptions;
diff --git a/riscv/insns/madd_s.h b/riscv/insns/madd_s.h
deleted file mode 100644
index 19db642..0000000
--- a/riscv/insns/madd_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3);
-set_fp_exceptions;
diff --git a/riscv/insns/msub_d.h b/riscv/insns/msub_d.h
deleted file mode 100644
index b1e9340..0000000
--- a/riscv/insns/msub_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN);
-set_fp_exceptions;
diff --git a/riscv/insns/msub_s.h b/riscv/insns/msub_s.h
deleted file mode 100644
index d3349f5..0000000
--- a/riscv/insns/msub_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN);
-set_fp_exceptions;
diff --git a/riscv/insns/mul_d.h b/riscv/insns/mul_d.h
deleted file mode 100644
index a8adedd..0000000
--- a/riscv/insns/mul_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mul(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/mul_s.h b/riscv/insns/mul_s.h
deleted file mode 100644
index 6475578..0000000
--- a/riscv/insns/mul_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mul(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/nmadd_d.h b/riscv/insns/nmadd_d.h
deleted file mode 100644
index 1e2ee27..0000000
--- a/riscv/insns/nmadd_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3) ^ (uint64_t)INT64_MIN;
-set_fp_exceptions;
diff --git a/riscv/insns/nmadd_s.h b/riscv/insns/nmadd_s.h
deleted file mode 100644
index 78abb78..0000000
--- a/riscv/insns/nmadd_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3) ^ (uint32_t)INT32_MIN;
-set_fp_exceptions;
diff --git a/riscv/insns/nmsub_d.h b/riscv/insns/nmsub_d.h
deleted file mode 100644
index ae643a5..0000000
--- a/riscv/insns/nmsub_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
-set_fp_exceptions;
diff --git a/riscv/insns/nmsub_s.h b/riscv/insns/nmsub_s.h
deleted file mode 100644
index cbb70ba..0000000
--- a/riscv/insns/nmsub_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_mulAdd(FRS1, FRS2, FRS3 ^ (uint32_t)INT32_MIN) ^ (uint32_t)INT32_MIN;
-set_fp_exceptions;
diff --git a/riscv/insns/s_b.h b/riscv/insns/s_b.h
new file mode 100644
index 0000000..af5bd10
--- /dev/null
+++ b/riscv/insns/s_b.h
@@ -0,0 +1 @@
+mmu.store_uint8(RS1+BIMM, RS2);
diff --git a/riscv/insns/s_d.h b/riscv/insns/s_d.h
index 113398e..2009149 100644
--- a/riscv/insns/s_d.h
+++ b/riscv/insns/s_d.h
@@ -1,2 +1,2 @@
-require_fp;
-mmu.store_uint64(RS1+BIMM, FRS2);
+require_xpr64;
+mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/s_h.h b/riscv/insns/s_h.h
new file mode 100644
index 0000000..a484e1e
--- /dev/null
+++ b/riscv/insns/s_h.h
@@ -0,0 +1 @@
+mmu.store_uint16(RS1+BIMM, RS2);
diff --git a/riscv/insns/s_s.h b/riscv/insns/s_s.h
deleted file mode 100644
index 23d3333..0000000
--- a/riscv/insns/s_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-mmu.store_uint32(RS1+BIMM, FRS2);
diff --git a/riscv/insns/s_w.h b/riscv/insns/s_w.h
new file mode 100644
index 0000000..dbe260f
--- /dev/null
+++ b/riscv/insns/s_w.h
@@ -0,0 +1 @@
+mmu.store_uint32(RS1+BIMM, RS2);
diff --git a/riscv/insns/sb.h b/riscv/insns/sb.h
deleted file mode 100644
index af5bd10..0000000
--- a/riscv/insns/sb.h
+++ /dev/null
@@ -1 +0,0 @@
-mmu.store_uint8(RS1+BIMM, RS2);
diff --git a/riscv/insns/sd.h b/riscv/insns/sd.h
deleted file mode 100644
index 2009149..0000000
--- a/riscv/insns/sd.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_xpr64;
-mmu.store_uint64(RS1+BIMM, RS2);
diff --git a/riscv/insns/sf_d.h b/riscv/insns/sf_d.h
new file mode 100644
index 0000000..113398e
--- /dev/null
+++ b/riscv/insns/sf_d.h
@@ -0,0 +1,2 @@
+require_fp;
+mmu.store_uint64(RS1+BIMM, FRS2);
diff --git a/riscv/insns/sf_w.h b/riscv/insns/sf_w.h
new file mode 100644
index 0000000..23d3333
--- /dev/null
+++ b/riscv/insns/sf_w.h
@@ -0,0 +1,2 @@
+require_fp;
+mmu.store_uint32(RS1+BIMM, FRS2);
diff --git a/riscv/insns/sgninj_d.h b/riscv/insns/sgninj_d.h
deleted file mode 100644
index f66e804..0000000
--- a/riscv/insns/sgninj_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ INT64_MIN) | (FRS2 & INT64_MIN);
diff --git a/riscv/insns/sgninj_s.h b/riscv/insns/sgninj_s.h
deleted file mode 100644
index 35609ac..0000000
--- a/riscv/insns/sgninj_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/sgninjn_d.h b/riscv/insns/sgninjn_d.h
deleted file mode 100644
index 22de215..0000000
--- a/riscv/insns/sgninjn_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ INT64_MIN) | ((~FRS2) & INT64_MIN);
diff --git a/riscv/insns/sgninjn_s.h b/riscv/insns/sgninjn_s.h
deleted file mode 100644
index dd66d71..0000000
--- a/riscv/insns/sgninjn_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = (FRS1 &~ (uint32_t)INT32_MIN) | ((~FRS2) & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/sgnmul_d.h b/riscv/insns/sgnmul_d.h
deleted file mode 100644
index 331b6e4..0000000
--- a/riscv/insns/sgnmul_d.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = FRS1 ^ (FRS2 & INT64_MIN);
diff --git a/riscv/insns/sgnmul_s.h b/riscv/insns/sgnmul_s.h
deleted file mode 100644
index b455406..0000000
--- a/riscv/insns/sgnmul_s.h
+++ /dev/null
@@ -1,2 +0,0 @@
-require_fp;
-FRD = FRS1 ^ (FRS2 & (uint32_t)INT32_MIN);
diff --git a/riscv/insns/sh.h b/riscv/insns/sh.h
deleted file mode 100644
index a484e1e..0000000
--- a/riscv/insns/sh.h
+++ /dev/null
@@ -1 +0,0 @@
-mmu.store_uint16(RS1+BIMM, RS2);
diff --git a/riscv/insns/sqrt_d.h b/riscv/insns/sqrt_d.h
deleted file mode 100644
index 7647c9c..0000000
--- a/riscv/insns/sqrt_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_sqrt(FRS1);
-set_fp_exceptions;
diff --git a/riscv/insns/sqrt_s.h b/riscv/insns/sqrt_s.h
deleted file mode 100644
index 426f241..0000000
--- a/riscv/insns/sqrt_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_sqrt(FRS1);
-set_fp_exceptions;
diff --git a/riscv/insns/sub_d.h b/riscv/insns/sub_d.h
deleted file mode 100644
index e25eebb..0000000
--- a/riscv/insns/sub_d.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f64_sub(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/sub_s.h b/riscv/insns/sub_s.h
deleted file mode 100644
index 6c64d04..0000000
--- a/riscv/insns/sub_s.h
+++ /dev/null
@@ -1,4 +0,0 @@
-require_fp;
-softfloat_roundingMode = RM;
-FRD = f32_sub(FRS1, FRS2);
-set_fp_exceptions;
diff --git a/riscv/insns/sw.h b/riscv/insns/sw.h
deleted file mode 100644
index dbe260f..0000000
--- a/riscv/insns/sw.h
+++ /dev/null
@@ -1 +0,0 @@
-mmu.store_uint32(RS1+BIMM, RS2);