From: lkcl Date: Thu, 23 Jan 2020 14:08:15 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~3763 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0100003f9fbd1ab461f3101a69bfa5454177cce;p=libreriscv.git --- diff --git a/HDL_workflow.mdwn b/HDL_workflow.mdwn index 663296d3c..3a9e574e3 100644 --- a/HDL_workflow.mdwn +++ b/HDL_workflow.mdwn @@ -148,3 +148,6 @@ The reasons for doing a proper modularisation job are several-fold: Find appropriate tutorials for nmigen and yosys, as well as symbiyosys. * Although a verilog example this is very useful to do +* There exist several nmigen examples which are also executable +* This tutorial looks pretty good and will get you started and walks not just through simulation, it takes you through using gtkwave as well. +