From: Clifford Wolf Date: Fri, 7 Jun 2019 11:12:25 +0000 (+0200) Subject: Rename implicit_ports.sv test to implicit_ports.v X-Git-Tag: yosys-0.9~81 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f01a61f093528e5111e5dac8aedbf8c7c468be1c;p=yosys.git Rename implicit_ports.sv test to implicit_ports.v Signed-off-by: Clifford Wolf --- diff --git a/tests/simple/implicit_ports.sv b/tests/simple/implicit_ports.sv deleted file mode 100644 index 8b0a6f386..000000000 --- a/tests/simple/implicit_ports.sv +++ /dev/null @@ -1,16 +0,0 @@ -// Test implicit port connections -module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); - assign cout = cin; - assign result = a + b; -endmodule - -module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); - wire cin = 1; - alu alu ( - .a(a), - .b, // Implicit connection is equivalent to .b(b) - .cin(), // Explicitely unconnected - .cout(cout), - .result(alu_result) - ); -endmodule diff --git a/tests/simple/implicit_ports.v b/tests/simple/implicit_ports.v new file mode 100644 index 000000000..8b0a6f386 --- /dev/null +++ b/tests/simple/implicit_ports.v @@ -0,0 +1,16 @@ +// Test implicit port connections +module alu (input [2:0] a, input [2:0] b, input cin, output cout, output [2:0] result); + assign cout = cin; + assign result = a + b; +endmodule + +module named_ports(input [2:0] a, b, output [2:0] alu_result, output cout); + wire cin = 1; + alu alu ( + .a(a), + .b, // Implicit connection is equivalent to .b(b) + .cin(), // Explicitely unconnected + .cout(cout), + .result(alu_result) + ); +endmodule