From: R Veera Kumar <vklr@vkten.in>
Date: Mon, 22 Nov 2021 02:18:06 +0000 (+0530)
Subject: Add expected state to case_addme_ca_so_3 in alu_cases unit test
X-Git-Tag: sv_maxu_works-initial~721
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f01e9a0b4b5037cfe94e8b1b0b94343844ef910a;p=openpower-isa.git

Add expected state to case_addme_ca_so_3 in alu_cases unit test
---

diff --git a/src/openpower/test/alu/alu_cases.py b/src/openpower/test/alu/alu_cases.py
index e9353622..71e45c2f 100644
--- a/src/openpower/test/alu/alu_cases.py
+++ b/src/openpower/test/alu/alu_cases.py
@@ -159,8 +159,14 @@ class ALUTestCase(TestAccumulatorBase):
         xer[XER_bits['CA']] = 1
         xer[XER_bits['SO']] = 1
         initial_sprs[special_sprs['XER']] = xer
+        e = ExpectedState(pc=4)
+        e.intregs[16] = 0x7ffffffff
+        e.intregs[6] = 0x7ffffffff
+        e.crregs[0] = 0x5
+        e.so = 0x1
+        e.ca = 0x3
         self.add_case(Program(lst, bigendian),
-                      initial_regs, initial_sprs)
+                      initial_regs, initial_sprs, expected=e)
 
     def case_addze(self):
         insns = ["addze", "addze.", "addzeo", "addzeo."]