From: yimmanuel3@f4ac60d763911c3fa518755176e4b9ed455c75d8 Date: Sun, 2 Feb 2020 09:07:06 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~3614 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f03659693fa4de4a57f9beace861f3e3fe160292;p=libreriscv.git --- diff --git a/index.mdwn b/index.mdwn index 75100710e..0cce282e4 100644 --- a/index.mdwn +++ b/index.mdwn @@ -19,7 +19,7 @@ Its entirely possible that you're OK with the fact that modern processors have [backdoors](https://www.csoonline.com/article/3220476/researchers-say-now-you-too-can-disable-intel-me-backdoor-thanks-to-the-nsa.html) that bad actors regularly exploit. -But beyond the contemporary ever increasing cry for privacy, is a very real need for reliable safety critical processors. +But beyond the contemporary ever increasing cry for privacy, is a very real need for reliable safety critical processors(think airplane, smart car, pacemaker...). LibreSOC poses to you that it is impossible to trust a processor in a safety critical environment without both access to that processor's source and a cycle accurate HDL simulator that guarantees developers their code behaves as they expect. An ISA level simulator is no longer satisfactory.