From: Jason Ekstrand Date: Tue, 17 Nov 2015 15:07:02 +0000 (-0800) Subject: anv: Add initial Haswell support X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0390bcad6b5e1f1e94bbf762ccc98bf499c022b;p=mesa.git anv: Add initial Haswell support --- diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am index 6e4de53b2d0..c484f2d92d6 100644 --- a/src/vulkan/Makefile.am +++ b/src/vulkan/Makefile.am @@ -34,6 +34,12 @@ lib_LTLIBRARIES = libvulkan.la check_LTLIBRARIES = libvulkan-test.la +PER_GEN_LIBS = \ + libanv-gen7.la \ + libanv-gen75.la + +noinst_LTLIBRARIES = $(PER_GEN_LIBS) + # The gallium includes are for the util/u_math.h include from main/macros.h AM_CPPFLAGS = \ @@ -81,9 +87,6 @@ VULKAN_SOURCES = \ gen8_state.c \ gen8_cmd_buffer.c \ gen8_pipeline.c \ - gen7_state.c \ - gen7_cmd_buffer.c \ - gen7_pipeline.c \ isl.c \ isl_format_layout.c @@ -92,6 +95,18 @@ BUILT_SOURCES = \ anv_entrypoints.c \ isl_format_layout.c +libanv_gen7_la_SOURCES = \ + gen7_cmd_buffer.c \ + gen7_pipeline.c \ + gen7_state.c +libanv_gen7_la_CFLAGS = $(libvulkan_la_CFLAGS) -DANV_GENx10=70 + +libanv_gen75_la_SOURCES = \ + gen7_cmd_buffer.c \ + gen7_pipeline.c \ + gen7_state.c +libanv_gen75_la_CFLAGS = $(libvulkan_la_CFLAGS) -DANV_GENx10=75 + if HAVE_EGL_PLATFORM_WAYLAND BUILT_SOURCES += \ wayland-drm-protocol.c \ @@ -131,7 +146,8 @@ libvulkan_la_LIBADD = $(WAYLAND_LIBS) -lxcb -lxcb-dri3 \ $(top_builddir)/src/mesa/drivers/dri/i965/libi965_compiler.la \ ../mesa/libmesa.la \ ../mesa/drivers/dri/common/libdri_test_stubs.la \ - -lpthread -ldl -lstdc++ + -lpthread -ldl -lstdc++ \ + $(PER_GEN_LIBS) # Libvulkan with dummy gem. Used for unit tests. diff --git a/src/vulkan/anv_device.c b/src/vulkan/anv_device.c index 0643944fa23..406792af95e 100644 --- a/src/vulkan/anv_device.c +++ b/src/vulkan/anv_device.c @@ -83,8 +83,9 @@ anv_physical_device_init(struct anv_physical_device *device, goto fail; } - if (device->info->gen == 7 && - !device->info->is_haswell && !device->info->is_baytrail) { + if (device->info->is_haswell) { + fprintf(stderr, "WARNING: Haswell Vulkan support is incomplete\n"); + } else if (device->info->gen == 7 && !device->info->is_baytrail) { fprintf(stderr, "WARNING: Ivy Bridge Vulkan support is incomplete\n"); } else if (device->info->gen == 8 && !device->info->is_cherryview) { /* Briadwell is as fully supported as anything */ @@ -1439,7 +1440,10 @@ anv_fill_buffer_surface_state(struct anv_device *device, void *state, { switch (device->info.gen) { case 7: - gen7_fill_buffer_surface_state(state, format, offset, range, stride); + if (device->info.is_haswell) + gen75_fill_buffer_surface_state(state, format, offset, range, stride); + else + gen7_fill_buffer_surface_state(state, format, offset, range, stride); break; case 8: gen8_fill_buffer_surface_state(state, format, offset, range, stride); diff --git a/src/vulkan/anv_image.c b/src/vulkan/anv_image.c index 7808454262e..60d23a17f5f 100644 --- a/src/vulkan/anv_image.c +++ b/src/vulkan/anv_image.c @@ -565,7 +565,10 @@ anv_image_view_init(struct anv_image_view *iview, switch (device->info.gen) { case 7: - gen7_image_view_init(iview, device, pCreateInfo, cmd_buffer); + if (device->info.is_haswell) + gen75_image_view_init(iview, device, pCreateInfo, cmd_buffer); + else + gen7_image_view_init(iview, device, pCreateInfo, cmd_buffer); break; case 8: gen8_image_view_init(iview, device, pCreateInfo, cmd_buffer); diff --git a/src/vulkan/anv_pipeline.c b/src/vulkan/anv_pipeline.c index 6c9deaddda7..597188c5f24 100644 --- a/src/vulkan/anv_pipeline.c +++ b/src/vulkan/anv_pipeline.c @@ -1087,7 +1087,10 @@ anv_graphics_pipeline_create( switch (device->info.gen) { case 7: - return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline); + if (device->info.is_haswell) + return gen75_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline); + else + return gen7_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline); case 8: return gen8_graphics_pipeline_create(_device, pCreateInfo, extra, pPipeline); default: @@ -1129,7 +1132,10 @@ static VkResult anv_compute_pipeline_create( switch (device->info.gen) { case 7: - return gen7_compute_pipeline_create(_device, pCreateInfo, pPipeline); + if (device->info.is_haswell) + return gen75_compute_pipeline_create(_device, pCreateInfo, pPipeline); + else + return gen7_compute_pipeline_create(_device, pCreateInfo, pPipeline); case 8: return gen8_compute_pipeline_create(_device, pCreateInfo, pPipeline); default: diff --git a/src/vulkan/anv_private.h b/src/vulkan/anv_private.h index a074ecda751..03e05fcb238 100644 --- a/src/vulkan/anv_private.h +++ b/src/vulkan/anv_private.h @@ -677,6 +677,11 @@ __gen_combine_address(struct anv_batch *batch, void *location, .L3CacheabilityControlL3CC = 1, \ } +#define GEN75_MOCS (struct GEN75_MEMORY_OBJECT_CONTROL_STATE) { \ + .LLCeLLCCacheabilityControlLLCCC = 0, \ + .L3CacheabilityControlL3CC = 1, \ +} + #define GEN8_MOCS { \ .MemoryTypeLLCeLLCCacheabilityControl = WB, \ .TargetCache = L3DefertoPATforLLCeLLCselection, \ @@ -1198,6 +1203,12 @@ gen7_graphics_pipeline_create(VkDevice _device, const struct anv_graphics_pipeline_create_info *extra, VkPipeline *pPipeline); +VkResult +gen75_graphics_pipeline_create(VkDevice _device, + const VkGraphicsPipelineCreateInfo *pCreateInfo, + const struct anv_graphics_pipeline_create_info *extra, + VkPipeline *pPipeline); + VkResult gen8_graphics_pipeline_create(VkDevice _device, const VkGraphicsPipelineCreateInfo *pCreateInfo, @@ -1207,6 +1218,10 @@ VkResult gen7_compute_pipeline_create(VkDevice _device, const VkComputePipelineCreateInfo *pCreateInfo, VkPipeline *pPipeline); +VkResult +gen75_compute_pipeline_create(VkDevice _device, + const VkComputePipelineCreateInfo *pCreateInfo, + VkPipeline *pPipeline); VkResult gen8_compute_pipeline_create(VkDevice _device, @@ -1363,6 +1378,12 @@ gen7_image_view_init(struct anv_image_view *iview, const VkImageViewCreateInfo* pCreateInfo, struct anv_cmd_buffer *cmd_buffer); +void +gen75_image_view_init(struct anv_image_view *iview, + struct anv_device *device, + const VkImageViewCreateInfo* pCreateInfo, + struct anv_cmd_buffer *cmd_buffer); + void gen8_image_view_init(struct anv_image_view *iview, struct anv_device *device, @@ -1377,6 +1398,9 @@ void anv_fill_buffer_surface_state(struct anv_device *device, void *state, void gen7_fill_buffer_surface_state(void *state, const struct anv_format *format, uint32_t offset, uint32_t range, uint32_t stride); +void gen75_fill_buffer_surface_state(void *state, const struct anv_format *format, + uint32_t offset, uint32_t range, + uint32_t stride); void gen8_fill_buffer_surface_state(void *state, const struct anv_format *format, uint32_t offset, uint32_t range, uint32_t stride); diff --git a/src/vulkan/gen7_cmd_buffer.c b/src/vulkan/gen7_cmd_buffer.c index 4f5d50fe167..61592111fca 100644 --- a/src/vulkan/gen7_cmd_buffer.c +++ b/src/vulkan/gen7_cmd_buffer.c @@ -30,9 +30,10 @@ #include "anv_private.h" #include "gen7_pack.h" +#include "gen75_pack.h" static void -gen7_cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer) +cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer) { static const uint32_t push_constant_opcodes[] = { [VK_SHADER_STAGE_VERTEX] = 21, @@ -65,9 +66,8 @@ gen7_cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->state.push_constants_dirty &= ~flushed; } - -void -gen7_cmd_buffer_emit_state_base_address(struct anv_cmd_buffer *cmd_buffer) +GENX_FUNC(GEN7, GEN7) void +genX(cmd_buffer_emit_state_base_address)(struct anv_cmd_buffer *cmd_buffer) { struct anv_device *device = cmd_buffer->device; struct anv_bo *scratch_bo = NULL; @@ -198,8 +198,8 @@ flush_descriptor_set(struct anv_cmd_buffer *cmd_buffer, VkShaderStage stage) return VK_SUCCESS; } -void -gen7_cmd_buffer_flush_descriptor_sets(struct anv_cmd_buffer *cmd_buffer) +GENX_FUNC(GEN7, GEN7) void +genX(cmd_buffer_flush_descriptor_sets)(struct anv_cmd_buffer *cmd_buffer) { VkShaderStage s; VkShaderStageFlags dirty = cmd_buffer->state.descriptors_dirty & @@ -289,8 +289,8 @@ emit_scissor_state(struct anv_cmd_buffer *cmd_buffer, .ScissorRectPointer = scissor_state.offset); } -void -gen7_cmd_buffer_emit_scissor(struct anv_cmd_buffer *cmd_buffer) +GENX_FUNC(GEN7, GEN7) void +genX(cmd_buffer_emit_scissor)(struct anv_cmd_buffer *cmd_buffer) { if (cmd_buffer->state.dynamic.scissor.count > 0) { emit_scissor_state(cmd_buffer, cmd_buffer->state.dynamic.scissor.count, @@ -313,7 +313,12 @@ static const uint32_t vk_to_gen_index_type[] = { [VK_INDEX_TYPE_UINT32] = INDEX_DWORD, }; -void gen7_CmdBindIndexBuffer( +static const uint32_t restart_index_for_type[] = { + [VK_INDEX_TYPE_UINT16] = UINT16_MAX, + [VK_INDEX_TYPE_UINT32] = UINT32_MAX, +}; + +void genX(CmdBindIndexBuffer)( VkCmdBuffer cmdBuffer, VkBuffer _buffer, VkDeviceSize offset, @@ -323,13 +328,15 @@ void gen7_CmdBindIndexBuffer( ANV_FROM_HANDLE(anv_buffer, buffer, _buffer); cmd_buffer->state.dirty |= ANV_CMD_DIRTY_INDEX_BUFFER; + if (ANV_IS_HASWELL) + cmd_buffer->state.restart_index = restart_index_for_type[indexType]; cmd_buffer->state.gen7.index_buffer = buffer; cmd_buffer->state.gen7.index_type = vk_to_gen_index_type[indexType]; cmd_buffer->state.gen7.index_offset = offset; } static VkResult -gen7_flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer) +flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer) { struct anv_device *device = cmd_buffer->device; struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; @@ -366,7 +373,7 @@ gen7_flush_compute_descriptor_set(struct anv_cmd_buffer *cmd_buffer) } static void -gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer) +cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer) { struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; VkResult result; @@ -385,7 +392,7 @@ gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer) if ((cmd_buffer->state.descriptors_dirty & VK_SHADER_STAGE_COMPUTE_BIT) || (cmd_buffer->state.compute_dirty & ANV_CMD_DIRTY_PIPELINE)) { /* FIXME: figure out descriptors for gen7 */ - result = gen7_flush_compute_descriptor_set(cmd_buffer); + result = flush_compute_descriptor_set(cmd_buffer); assert(result == VK_SUCCESS); cmd_buffer->state.descriptors_dirty &= ~VK_SHADER_STAGE_COMPUTE; } @@ -394,7 +401,7 @@ gen7_cmd_buffer_flush_compute_state(struct anv_cmd_buffer *cmd_buffer) } static void -gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer) +cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer) { struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; uint32_t *p; @@ -469,7 +476,7 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer) gen7_cmd_buffer_flush_descriptor_sets(cmd_buffer); if (cmd_buffer->state.push_constants_dirty) - gen7_cmd_buffer_flush_push_constants(cmd_buffer); + cmd_buffer_flush_push_constants(cmd_buffer); /* We use the gen8 state here because it only contains the additional * min/max fields and, since they occur at the end of the packet and @@ -564,6 +571,12 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer) struct anv_buffer *buffer = cmd_buffer->state.gen7.index_buffer; uint32_t offset = cmd_buffer->state.gen7.index_offset; + if (ANV_IS_HASWELL) { + anv_batch_emit(&cmd_buffer->batch, GEN75_3DSTATE_VF, + .IndexedDrawCutIndexEnable = pipeline->primitive_restart, + .CutIndex = cmd_buffer->state.restart_index); + } + anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_INDEX_BUFFER, .CutIndexEnable = pipeline->primitive_restart, .IndexFormat = cmd_buffer->state.gen7.index_type, @@ -576,7 +589,7 @@ gen7_cmd_buffer_flush_state(struct anv_cmd_buffer *cmd_buffer) cmd_buffer->state.dirty = 0; } -void gen7_CmdDraw( +void genX(CmdDraw)( VkCmdBuffer cmdBuffer, uint32_t vertexCount, uint32_t instanceCount, @@ -586,7 +599,7 @@ void gen7_CmdDraw( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer); struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; - gen7_cmd_buffer_flush_state(cmd_buffer); + cmd_buffer_flush_state(cmd_buffer); anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE, .VertexAccessType = SEQUENTIAL, @@ -598,7 +611,7 @@ void gen7_CmdDraw( .BaseVertexLocation = 0); } -void gen7_CmdDrawIndexed( +void genX(CmdDrawIndexed)( VkCmdBuffer cmdBuffer, uint32_t indexCount, uint32_t instanceCount, @@ -609,7 +622,7 @@ void gen7_CmdDrawIndexed( ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer); struct anv_pipeline *pipeline = cmd_buffer->state.pipeline; - gen7_cmd_buffer_flush_state(cmd_buffer); + cmd_buffer_flush_state(cmd_buffer); anv_batch_emit(&cmd_buffer->batch, GEN7_3DPRIMITIVE, .VertexAccessType = RANDOM, @@ -646,7 +659,7 @@ gen7_batch_lri(struct anv_batch *batch, uint32_t reg, uint32_t imm) #define GEN7_3DPRIM_START_INSTANCE 0x243C #define GEN7_3DPRIM_BASE_VERTEX 0x2440 -void gen7_CmdDrawIndirect( +void genX(CmdDrawIndirect)( VkCmdBuffer cmdBuffer, VkBuffer _buffer, VkDeviceSize offset, @@ -659,7 +672,7 @@ void gen7_CmdDrawIndirect( struct anv_bo *bo = buffer->bo; uint32_t bo_offset = buffer->offset + offset; - gen7_cmd_buffer_flush_state(cmd_buffer); + cmd_buffer_flush_state(cmd_buffer); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4); @@ -673,7 +686,7 @@ void gen7_CmdDrawIndirect( .PrimitiveTopologyType = pipeline->topology); } -void gen7_CmdDrawIndexedIndirect( +void genX(CmdDrawIndexedIndirect)( VkCmdBuffer cmdBuffer, VkBuffer _buffer, VkDeviceSize offset, @@ -686,7 +699,7 @@ void gen7_CmdDrawIndexedIndirect( struct anv_bo *bo = buffer->bo; uint32_t bo_offset = buffer->offset + offset; - gen7_cmd_buffer_flush_state(cmd_buffer); + cmd_buffer_flush_state(cmd_buffer); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_VERTEX_COUNT, bo, bo_offset); gen7_batch_lrm(&cmd_buffer->batch, GEN7_3DPRIM_INSTANCE_COUNT, bo, bo_offset + 4); @@ -700,7 +713,7 @@ void gen7_CmdDrawIndexedIndirect( .PrimitiveTopologyType = pipeline->topology); } -void gen7_CmdDispatch( +void genX(CmdDispatch)( VkCmdBuffer cmdBuffer, uint32_t x, uint32_t y, @@ -710,7 +723,7 @@ void gen7_CmdDispatch( struct anv_pipeline *pipeline = cmd_buffer->state.compute_pipeline; struct brw_cs_prog_data *prog_data = &pipeline->cs_prog_data; - gen7_cmd_buffer_flush_compute_state(cmd_buffer); + cmd_buffer_flush_compute_state(cmd_buffer); anv_batch_emit(&cmd_buffer->batch, GEN7_GPGPU_WALKER, .SIMDSize = prog_data->simd_size / 16, @@ -730,7 +743,7 @@ void gen7_CmdDispatch( #define GPGPU_DISPATCHDIMY 0x2504 #define GPGPU_DISPATCHDIMZ 0x2508 -void gen7_CmdDispatchIndirect( +void genX(CmdDispatchIndirect)( VkCmdBuffer cmdBuffer, VkBuffer _buffer, VkDeviceSize offset) @@ -742,7 +755,7 @@ void gen7_CmdDispatchIndirect( struct anv_bo *bo = buffer->bo; uint32_t bo_offset = buffer->offset + offset; - gen7_cmd_buffer_flush_compute_state(cmd_buffer); + cmd_buffer_flush_compute_state(cmd_buffer); gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMX, bo, bo_offset); gen7_batch_lrm(&cmd_buffer->batch, GPGPU_DISPATCHDIMY, bo, bo_offset + 4); @@ -760,7 +773,7 @@ void gen7_CmdDispatchIndirect( anv_batch_emit(&cmd_buffer->batch, GEN7_MEDIA_STATE_FLUSH); } -void gen7_CmdPipelineBarrier( +void genX(CmdPipelineBarrier)( VkCmdBuffer cmdBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags destStageMask, @@ -772,7 +785,7 @@ void gen7_CmdPipelineBarrier( } static void -gen7_cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) +cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) { const struct anv_framebuffer *fb = cmd_buffer->state.framebuffer; const struct anv_image_view *iview = @@ -854,14 +867,14 @@ gen7_cmd_buffer_emit_depth_stencil(struct anv_cmd_buffer *cmd_buffer) anv_batch_emit(&cmd_buffer->batch, GEN7_3DSTATE_CLEAR_PARAMS); } -void -gen7_cmd_buffer_begin_subpass(struct anv_cmd_buffer *cmd_buffer, - struct anv_subpass *subpass) +GENX_FUNC(GEN7, GEN7) void +genX(cmd_buffer_begin_subpass)(struct anv_cmd_buffer *cmd_buffer, + struct anv_subpass *subpass) { cmd_buffer->state.subpass = subpass; cmd_buffer->state.descriptors_dirty |= VK_SHADER_STAGE_FRAGMENT_BIT; - gen7_cmd_buffer_emit_depth_stencil(cmd_buffer); + cmd_buffer_emit_depth_stencil(cmd_buffer); } static void @@ -890,7 +903,7 @@ begin_render_pass(struct anv_cmd_buffer *cmd_buffer, pRenderPassBegin->pClearValues); } -void gen7_CmdBeginRenderPass( +void genX(CmdBeginRenderPass)( VkCmdBuffer cmdBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkRenderPassContents contents) @@ -903,7 +916,7 @@ void gen7_CmdBeginRenderPass( gen7_cmd_buffer_begin_subpass(cmd_buffer, pass->subpasses); } -void gen7_CmdNextSubpass( +void genX(CmdNextSubpass)( VkCmdBuffer cmdBuffer, VkRenderPassContents contents) { @@ -914,7 +927,7 @@ void gen7_CmdNextSubpass( gen7_cmd_buffer_begin_subpass(cmd_buffer, cmd_buffer->state.subpass + 1); } -void gen7_CmdEndRenderPass( +void genX(CmdEndRenderPass)( VkCmdBuffer cmdBuffer) { ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, cmdBuffer); diff --git a/src/vulkan/gen7_pipeline.c b/src/vulkan/gen7_pipeline.c index d53489c2db1..5e29df642da 100644 --- a/src/vulkan/gen7_pipeline.c +++ b/src/vulkan/gen7_pipeline.c @@ -30,6 +30,7 @@ #include "anv_private.h" #include "gen7_pack.h" +#include "gen75_pack.h" static void gen7_emit_vertex_input(struct anv_pipeline *pipeline, @@ -341,8 +342,8 @@ scratch_space(const struct brw_stage_prog_data *prog_data) return ffs(prog_data->total_scratch / 1024); } -VkResult -gen7_graphics_pipeline_create( +GENX_FUNC(GEN7, GEN75) VkResult +genX(graphics_pipeline_create)( VkDevice _device, const VkGraphicsPipelineCreateInfo* pCreateInfo, const struct anv_graphics_pipeline_create_info *extra, @@ -478,9 +479,9 @@ gen7_graphics_pipeline_create( #endif if (pipeline->vs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, .VSFunctionEnable = false); + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .VSFunctionEnable = false); else - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_VS, + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_VS), .KernelStartPointer = pipeline->vs_vec4, .ScratchSpaceBaseOffset = pipeline->scratch_start[VK_SHADER_STAGE_VERTEX], .PerThreadScratchSpace = scratch_space(&vue_prog_data->base), @@ -497,12 +498,12 @@ gen7_graphics_pipeline_create( const struct brw_gs_prog_data *gs_prog_data = &pipeline->gs_prog_data; if (pipeline->gs_vec4 == NO_KERNEL || (extra && extra->disable_vs)) { - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, .GSEnable = false); + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .GSEnable = false); } else { urb_offset = 1; urb_length = (gs_prog_data->base.vue_map.num_slots + 1) / 2 - urb_offset; - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_GS, + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_GS), .KernelStartPointer = pipeline->gs_vec4, .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_GEOMETRY], .PerThreadScratchSpace = scratch_space(&gs_prog_data->base.base), @@ -521,7 +522,11 @@ gen7_graphics_pipeline_create( .DispatchMode = gs_prog_data->base.dispatch_mode, .GSStatisticsEnable = true, .IncludePrimitiveID = gs_prog_data->include_primitive_id, +# if (ANV_IS_HASWELL) + .ReorderMode = REORDER_TRAILING, +# else .ReorderEnable = true, +# endif .GSEnable = true); } @@ -539,7 +544,7 @@ gen7_graphics_pipeline_create( .VertexURBEntryReadOffset = urb_offset, .PointSpriteTextureCoordinateOrigin = UPPERLEFT); - anv_batch_emit(&pipeline->batch, GEN7_3DSTATE_PS, + anv_batch_emit(&pipeline->batch, GENX(3DSTATE_PS), .KernelStartPointer0 = pipeline->ps_ksp0, .ScratchSpaceBasePointer = pipeline->scratch_start[VK_SHADER_STAGE_FRAGMENT], .PerThreadScratchSpace = scratch_space(&wm_prog_data->base), @@ -589,7 +594,8 @@ gen7_graphics_pipeline_create( return VK_SUCCESS; } -VkResult gen7_compute_pipeline_create( +GENX_FUNC(GEN7, GEN75) VkResult +genX(compute_pipeline_create)( VkDevice _device, const VkComputePipelineCreateInfo* pCreateInfo, VkPipeline* pPipeline) diff --git a/src/vulkan/gen7_state.c b/src/vulkan/gen7_state.c index 596e232ab6f..7adb4485b90 100644 --- a/src/vulkan/gen7_state.c +++ b/src/vulkan/gen7_state.c @@ -30,29 +30,37 @@ #include "anv_private.h" #include "gen7_pack.h" +#include "gen75_pack.h" -void -gen7_fill_buffer_surface_state(void *state, const struct anv_format *format, - uint32_t offset, uint32_t range, uint32_t stride) +GENX_FUNC(GEN7, GEN75) void +genX(fill_buffer_surface_state)(void *state, const struct anv_format *format, + uint32_t offset, uint32_t range, + uint32_t stride) { uint32_t num_elements = range / stride; - struct GEN7_RENDER_SURFACE_STATE surface_state = { + struct GENX(RENDER_SURFACE_STATE) surface_state = { .SurfaceType = SURFTYPE_BUFFER, .SurfaceFormat = format->surface_format, .SurfaceVerticalAlignment = VALIGN_4, .SurfaceHorizontalAlignment = HALIGN_4, .TiledSurface = false, .RenderCacheReadWriteMode = false, - .SurfaceObjectControlState = GEN7_MOCS, + .SurfaceObjectControlState = GENX(MOCS), .Height = (num_elements >> 7) & 0x3fff, .Width = num_elements & 0x7f, .Depth = (num_elements >> 21) & 0x3f, .SurfacePitch = stride - 1, +# if (ANV_IS_HASWELL) + .ShaderChannelSelectR = SCS_RED, + .ShaderChannelSelectG = SCS_GREEN, + .ShaderChannelSelectB = SCS_BLUE, + .ShaderChannelSelectA = SCS_ALPHA, +# endif .SurfaceBaseAddress = { NULL, offset }, }; - GEN7_RENDER_SURFACE_STATE_pack(NULL, state, &surface_state); + GENX(RENDER_SURFACE_STATE_pack)(NULL, state, &surface_state); } static const uint32_t vk_to_gen_tex_filter[] = { @@ -86,8 +94,8 @@ static const uint32_t vk_to_gen_compare_op[] = { }; static struct anv_state -gen7_alloc_surface_state(struct anv_device *device, - struct anv_cmd_buffer *cmd_buffer) +alloc_surface_state(struct anv_device *device, + struct anv_cmd_buffer *cmd_buffer) { if (cmd_buffer) { return anv_cmd_buffer_alloc_surface_state(cmd_buffer); @@ -96,7 +104,7 @@ gen7_alloc_surface_state(struct anv_device *device, } } -VkResult gen7_CreateSampler( +VkResult genX(CreateSampler)( VkDevice _device, const VkSamplerCreateInfo* pCreateInfo, VkSampler* pSampler) @@ -174,11 +182,20 @@ static const uint8_t anv_valign[] = { [4] = VALIGN_4, }; -void -gen7_image_view_init(struct anv_image_view *iview, - struct anv_device *device, - const VkImageViewCreateInfo* pCreateInfo, - struct anv_cmd_buffer *cmd_buffer) +static const uint32_t vk_to_gen_swizzle[] = { + [VK_CHANNEL_SWIZZLE_ZERO] = SCS_ZERO, + [VK_CHANNEL_SWIZZLE_ONE] = SCS_ONE, + [VK_CHANNEL_SWIZZLE_R] = SCS_RED, + [VK_CHANNEL_SWIZZLE_G] = SCS_GREEN, + [VK_CHANNEL_SWIZZLE_B] = SCS_BLUE, + [VK_CHANNEL_SWIZZLE_A] = SCS_ALPHA +}; + +GENX_FUNC(GEN7, GEN75) void +genX(image_view_init)(struct anv_image_view *iview, + struct anv_device *device, + const VkImageViewCreateInfo* pCreateInfo, + struct anv_cmd_buffer *cmd_buffer) { ANV_FROM_HANDLE(anv_image, image, pCreateInfo->image); @@ -211,7 +228,7 @@ gen7_image_view_init(struct anv_image_view *iview, depth = image->extent.depth; } - struct GEN7_RENDER_SURFACE_STATE surface_state = { + struct GENX(RENDER_SURFACE_STATE) surface_state = { .SurfaceType = image->surface_type, .SurfaceArray = image->array_size > 1, .SurfaceFormat = format->surface_format, @@ -239,23 +256,29 @@ gen7_image_view_init(struct anv_image_view *iview, .XOffset = 0, .YOffset = 0, - .SurfaceObjectControlState = GEN7_MOCS, + .SurfaceObjectControlState = GENX(MOCS), .MIPCountLOD = 0, /* TEMPLATE */ .SurfaceMinLOD = 0, /* TEMPLATE */ .MCSEnable = false, +# if (ANV_IS_HASWELL) + .ShaderChannelSelectR = vk_to_gen_swizzle[pCreateInfo->channels.r], + .ShaderChannelSelectG = vk_to_gen_swizzle[pCreateInfo->channels.g], + .ShaderChannelSelectB = vk_to_gen_swizzle[pCreateInfo->channels.b], + .ShaderChannelSelectA = vk_to_gen_swizzle[pCreateInfo->channels.a], +# else /* XXX: Seriously? */ .RedClearColor = 0, .GreenClearColor = 0, .BlueClearColor = 0, .AlphaClearColor = 0, +# endif .ResourceMinLOD = 0.0, .SurfaceBaseAddress = { NULL, iview->offset }, }; if (image->needs_nonrt_surface_state) { - iview->nonrt_surface_state = - gen7_alloc_surface_state(device, cmd_buffer); + iview->nonrt_surface_state = alloc_surface_state(device, cmd_buffer); surface_state.RenderCacheReadWriteMode = false; @@ -266,13 +289,12 @@ gen7_image_view_init(struct anv_image_view *iview, surface_state.SurfaceMinLOD = range->baseMipLevel; surface_state.MIPCountLOD = range->mipLevels - 1; - GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->nonrt_surface_state.map, - &surface_state); + GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->nonrt_surface_state.map, + &surface_state); } if (image->needs_color_rt_surface_state) { - iview->color_rt_surface_state = - gen7_alloc_surface_state(device, cmd_buffer); + iview->color_rt_surface_state = alloc_surface_state(device, cmd_buffer); surface_state.RenderCacheReadWriteMode = 0; /* Write only */ @@ -285,7 +307,7 @@ gen7_image_view_init(struct anv_image_view *iview, surface_state.MIPCountLOD = range->baseMipLevel; surface_state.SurfaceMinLOD = 0; - GEN7_RENDER_SURFACE_STATE_pack(NULL, iview->color_rt_surface_state.map, - &surface_state); + GENX(RENDER_SURFACE_STATE_pack)(NULL, iview->color_rt_surface_state.map, + &surface_state); } }