From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 20 Mar 2020 22:36:29 +0000 (+0100)
Subject: targets: switch to add_ethernet method instead of EthernetSoC.
X-Git-Tag: 24jan2021_ls180~541
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f03d862c06e5cb8773df43d6799c7d135b8e183a;p=litex.git

targets: switch to add_ethernet method instead of EthernetSoC.
---

diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py
index 41e306fe..659d3d1c 100755
--- a/litex/boards/targets/arty.py
+++ b/litex/boards/targets/arty.py
@@ -19,7 +19,6 @@ from litedram.modules import MT41K128M16
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.mii import LiteEthPHYMII
-from liteeth.mac import LiteEthMAC
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.frontend.etherbone import LiteEthEtherbone
 
@@ -53,7 +52,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
         platform = arty.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -80,41 +79,13 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHYMII(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = self.cpu.endianness)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
-
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHYMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # EtherboneSoC -------------------------------------------------------------------------------------
 
@@ -159,10 +130,10 @@ def main():
     assert not (args.with_ethernet and args.with_etherbone)
     cls = BaseSoC
     if args.with_ethernet:
-        cls = EthernetSoC
+        cls = BaseSoC
     if args.with_etherbone:
         cls = EtherboneSoC
-    soc = cls(**soc_sdram_argdict(args))
+    soc = cls(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(**vivado_build_argdict(args))
 
diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py
index c8ddcde6..6160dc9f 100755
--- a/litex/boards/targets/genesys2.py
+++ b/litex/boards/targets/genesys2.py
@@ -18,7 +18,6 @@ from litedram.modules import MT41J256M16
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
-from liteeth.mac import LiteEthMAC
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.frontend.etherbone import LiteEthEtherbone
 
@@ -44,7 +43,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
         platform = genesys2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -70,40 +69,13 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHYRGMII(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = self.cpu.endianness)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHYRGMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # EtherboneSoC -------------------------------------------------------------------------------------
 
@@ -147,10 +119,10 @@ def main():
     assert not (args.with_ethernet and args.with_etherbone)
     cls = BaseSoC
     if args.with_ethernet:
-        cls = EthernetSoC
+        cls = BaseSoC
     if args.with_etherbone:
         cls = EtherboneSoC
-    soc = cls(**soc_sdram_argdict(args))
+    soc = cls(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 
diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py
index 3c6d2374..35a30c43 100755
--- a/litex/boards/targets/kc705.py
+++ b/litex/boards/targets/kc705.py
@@ -20,7 +20,6 @@ from litedram.modules import MT8JTF12864
 from litedram.phy import s7ddrphy
 
 from liteeth.phy import LiteEthPHY
-from liteeth.mac import LiteEthMAC
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -44,7 +43,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
         platform = kc705.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -72,41 +71,14 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHY(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"),
-            clk_freq   = self.clk_freq)
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = self.cpu.endianness)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHY(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"),
+                clk_freq   = self.clk_freq)
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -118,8 +90,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    soc = cls(**soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 
diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py
index 12693dd5..cd9beb19 100755
--- a/litex/boards/targets/kcu105.py
+++ b/litex/boards/targets/kcu105.py
@@ -18,7 +18,6 @@ from litedram.modules import EDY4016A
 from litedram.phy import usddrphy
 
 from liteeth.phy.ku_1000basex import KU_1000BASEX
-from liteeth.mac import LiteEthMAC
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -51,11 +50,11 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, **kwargs):
         platform = kcu105.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
+        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, with_ethernet=False, **kwargs)
 
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = _CRG(platform, sys_clk_freq)
@@ -79,42 +78,15 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
-            data_pads    = self.platform.request("sfp", 0),
-            sys_clk_freq = self.clk_freq)
-        self.add_csr("ethphy")
-        self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
-        self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = self.cpu.endianness)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.cd_eth_rx.clk,
-            self.ethphy.cd_eth_tx.clk)
+        if with_ethernet:
+            self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk,
+                data_pads    = self.platform.request("sfp", 0),
+                sys_clk_freq = self.clk_freq)
+            self.add_csr("ethphy")
+            self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1)
+            self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]")
+            self.add_ethernet(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -126,8 +98,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    soc = cls(**soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 
diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py
index e066d0f0..f163ae7d 100755
--- a/litex/boards/targets/netv2.py
+++ b/litex/boards/targets/netv2.py
@@ -18,7 +18,6 @@ from litedram.modules import K4B2G1646F
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.rmii import LiteEthPHYRMII
-from liteeth.mac import LiteEthMAC
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -47,7 +46,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
         platform = netv2.Platform()
 
         # SoCCore ---------------------------------------------------------------------------------
@@ -73,40 +72,13 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHYRMII(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = self.cpu.endianness)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/50e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/50e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHYRMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -118,8 +90,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    soc = cls(**soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 
diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py
index e3d9f4b3..677a20f0 100755
--- a/litex/boards/targets/nexys_video.py
+++ b/litex/boards/targets/nexys_video.py
@@ -18,7 +18,6 @@ from litedram.modules import MT41K256M16
 from litedram.phy import s7ddrphy
 
 from liteeth.phy.s7rgmii import LiteEthPHYRGMII
-from liteeth.mac import LiteEthMAC
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -46,7 +45,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
         platform = nexys_video.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -72,40 +71,13 @@ class BaseSoC(SoCCore):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, **kwargs):
-        BaseSoC.__init__(self, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHYRGMII(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(
-            phy        = self.ethphy,
-            dw         = 32,
-            interface  = "wishbone",
-            endianness = self.cpu.endianness)
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHYRGMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -117,8 +89,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    soc = cls(**soc_sdram_argdict(args))
+    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 
diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py
index 7250c98f..b7befc89 100755
--- a/litex/boards/targets/simple.py
+++ b/litex/boards/targets/simple.py
@@ -14,12 +14,11 @@ from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 
 from liteeth.phy import LiteEthPHY
-from liteeth.mac import LiteEthMAC
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, platform, **kwargs):
+    def __init__(self, platform, with_ethernet=False, **kwargs):
         sys_clk_freq = int(1e9/platform.default_clk_period)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -28,30 +27,14 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, platform, **kwargs):
-        BaseSoC.__init__(self, platform, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHY(
-            clock_pads = self.platform.request("eth_clocks"),
-            pads       = self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
-            interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHY(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"),
+                clk_freq   = self.clk_freq)
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -72,8 +55,7 @@ def main():
         platform = platform_module.Platform(toolchain=args.gateware_toolchain)
     else:
         platform = platform_module.Platform()
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    soc = cls(platform, **soc_core_argdict(args))
+    soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build()
 
diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 9edcd644..21181b11 100755
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -22,7 +22,6 @@ from litedram.modules import MT41K64M16
 from litedram.phy import ECP5DDRPHY
 
 from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
-from liteeth.mac import LiteEthMAC
 
 # CRG ----------------------------------------------------------------------------------------------
 
@@ -73,7 +72,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), with_ethernet=False, toolchain="trellis", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------
@@ -100,37 +99,13 @@ class BaseSoC(SoCSDRAM):
                 l2_cache_reverse        = True
             )
 
-# EthernetSoC --------------------------------------------------------------------------------------
-
-class EthernetSoC(BaseSoC):
-    mem_map = {
-        "ethmac": 0xb0000000,
-    }
-    mem_map.update(BaseSoC.mem_map)
-
-    def __init__(self, toolchain="trellis", **kwargs):
-        BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
-
         # Ethernet ---------------------------------------------------------------------------------
-        # phy
-        self.submodules.ethphy = LiteEthPHYRGMII(
-            self.platform.request("eth_clocks"),
-            self.platform.request("eth"))
-        self.add_csr("ethphy")
-        # mac
-        self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
-            interface="wishbone", endianness=self.cpu.endianness)
-        self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io")
-        self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000)
-        self.add_csr("ethmac")
-        self.add_interrupt("ethmac")
-        # timing constraints
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
-        self.platform.add_false_path_constraints(
-            self.crg.cd_sys.clk,
-            self.ethphy.crg.cd_eth_rx.clk,
-            self.ethphy.crg.cd_eth_tx.clk)
+        if with_ethernet:
+            self.submodules.ethphy = LiteEthPHYRGMII(
+                clock_pads = self.platform.request("eth_clocks"),
+                pads       = self.platform.request("eth"))
+            self.add_csr("ethphy")
+            self.add_ethernet(phy=self.ethphy)
 
 # Build --------------------------------------------------------------------------------------------
 
@@ -147,8 +122,7 @@ def main():
                         help="enable Ethernet support")
     args = parser.parse_args()
 
-    cls = EthernetSoC if args.with_ethernet else BaseSoC
-    soc = cls(toolchain=args.toolchain, sys_clk_freq=int(float(args.sys_clk_freq)), **soc_sdram_argdict(args))
+    soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)), with_ethernet=args.with_ethernet, toolchain=args.toolchain, **soc_sdram_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
     builder.build(**builder_kargs)
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 8b39d566..a070fbb3 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -1051,12 +1051,18 @@ class LiteXSoC(SoC):
         self.add_csr("ethmac")
         self.add_interrupt("ethmac")
         # Timing constraints
-        self.platform.add_period_constraint(phy.crg.cd_eth_rx.clk, 1e9/phy.rx_clk_freq)
-        self.platform.add_period_constraint(phy.crg.cd_eth_tx.clk, 1e9/phy.tx_clk_freq)
+        if hasattr(phy, "crg"):
+            eth_rx_clk = phy.crg.cd_eth_rx.clk
+            eth_tx_clk = phy.crg.cd_eth_tx.clk
+        else:
+            eth_rx_clk = phy.cd_eth_rx.clk
+            eth_tx_clk = phy.cd_eth_tx.clk
+        self.platform.add_period_constraint(eth_rx_clk, 1e9/phy.rx_clk_freq)
+        self.platform.add_period_constraint(eth_tx_clk, 1e9/phy.tx_clk_freq)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
-            phy.crg.cd_eth_rx.clk,
-            phy.crg.cd_eth_tx.clk)
+            eth_rx_clk,
+            eth_tx_clk)
 
     # Add SPI Flash --------------------------------------------------------------------------------
     def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):
diff --git a/test/test_targets.py b/test/test_targets.py
index d081d06c..4edfd291 100644
--- a/test/test_targets.py
+++ b/test/test_targets.py
@@ -45,13 +45,19 @@ class TestTargets(unittest.TestCase):
 
     # Artix-7
     def test_arty(self):
-        from litex.boards.targets.arty import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**test_kwargs), EthernetSoC(**test_kwargs)])
+        from litex.boards.targets.arty import BaseSoC
+        errors = build_test([
+            BaseSoC(**test_kwargs),
+            BaseSoC(with_ethernet=True, **test_kwargs)
+        ])
         self.assertEqual(errors, 0)
 
     def test_netv2(self):
-        from litex.boards.targets.netv2 import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**test_kwargs), EthernetSoC(**test_kwargs)])
+        from litex.boards.targets.netv2 import BaseSoC
+        errors = build_test([
+            BaseSoC(**test_kwargs),
+            BaseSoC(with_ethernet=True, **test_kwargs)
+        ])
         self.assertEqual(errors, 0)
 
     def test_nexys4ddr(self):
@@ -60,19 +66,28 @@ class TestTargets(unittest.TestCase):
         self.assertEqual(errors, 0)
 
     def test_nexys_video(self):
-        from litex.boards.targets.nexys_video import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**test_kwargs), EthernetSoC(**test_kwargs)])
+        from litex.boards.targets.nexys_video import BaseSoC
+        errors = build_test([
+            BaseSoC(**test_kwargs),
+            BaseSoC(with_ethernet=True, **test_kwargs)
+        ])
         self.assertEqual(errors, 0)
 
     # Kintex-7
     def test_genesys2(self):
-        from litex.boards.targets.genesys2 import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**test_kwargs), EthernetSoC(**test_kwargs)])
+        from litex.boards.targets.genesys2 import BaseSoC
+        errors = build_test([
+            BaseSoC(**test_kwargs),
+            BaseSoC(with_ethernet=True, **test_kwargs)
+        ])
         self.assertEqual(errors, 0)
 
     def test_kc705(self):
-        from litex.boards.targets.kc705 import BaseSoC, EthernetSoC
-        errors = build_test([BaseSoC(**test_kwargs), EthernetSoC(**test_kwargs)])
+        from litex.boards.targets.kc705 import BaseSoC
+        errors = build_test([
+            BaseSoC(**test_kwargs),
+            BaseSoC(with_ethernet=True, **test_kwargs)
+        ])
         self.assertEqual(errors, 0)
 
     # Kintex-Ultrascale