From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Nov 2021 16:41:00 +0000 (+0000)
Subject: whoops missed make_hazard_vec test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f04652574db96828d5a8250c772613ed72ba3b21;p=soc.git

whoops missed make_hazard_vec test
---

diff --git a/src/soc/simple/core.py b/src/soc/simple/core.py
index f73017c4..0f29a7f5 100644
--- a/src/soc/simple/core.py
+++ b/src/soc/simple/core.py
@@ -985,6 +985,9 @@ class NonProductionCore(ControlBase):
                 wvclrers[regfile.lower()].append(wvclren)
                 wvseters[regfile.lower()].append(wvseten)
 
+        if not self.make_hazard_vecs:
+            return
+
         # for write-vectors: reduce the clr-ers and set-ers down to
         # a single set of bits.  otherwise if there are two write
         # ports (on some regfiles), the last one doing comb += on
@@ -1091,6 +1094,7 @@ if __name__ == '__main__':
     pspec = TestMemPspec(ldst_ifacetype='testpi',
                          imem_ifacetype='',
                          addr_wid=48,
+                         allow_overlap=True,
                          mask_wid=8,
                          reg_wid=64)
     dut = NonProductionCore(pspec)