From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Tue, 24 Aug 2010 09:18:23 +0000 (-0700)
Subject: [sim] privileged mode support for 32-bit operation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f04bbaa997c5cf16d595ee452267d65cacb735fd;p=riscv-isa-sim.git

[sim] privileged mode support for 32-bit operation
---

diff --git a/riscv/insns/mfpcr.h b/riscv/insns/mfpcr.h
index 7808458..853842e 100644
--- a/riscv/insns/mfpcr.h
+++ b/riscv/insns/mfpcr.h
@@ -1,29 +1,32 @@
 require_supervisor;
-require64;
+
+reg_t val;
 
 switch(insn.rtype.rb)
 {
   case 0:
-    RA = sr;
+    val = sr;
     break;
   case 1:
-    RA = epc;
+    val = epc;
     break;
   case 2:
-    RA = badvaddr;
+    val = badvaddr;
     break;
   case 3:
-    RA = ebase;
+    val = ebase;
     break;
 
   case 8:
-    RA = MEMSIZE >> 12;
+    val = MEMSIZE >> 12;
     break;
 
   case 17:
-    RA = sim->get_fromhost();
+    val = sim->get_fromhost();
     break;
 
   default:
-    RA = -1;
+    val = -1;
 }
+
+RA = gprlen == 64 ? val : sext32(val);
diff --git a/riscv/insns/mtpcr.h b/riscv/insns/mtpcr.h
index 67195a6..01b3e2f 100644
--- a/riscv/insns/mtpcr.h
+++ b/riscv/insns/mtpcr.h
@@ -1,19 +1,20 @@
 require_supervisor;
-require64;
+
+reg_t val = gprlen == 64 ? RA : sext32(RA);
 
 switch(insn.rtype.rb)
 {
   case 0:
-    set_sr(RA);
+    set_sr(val);
     break;
   case 1:
-    epc = RA;
+    epc = val;
     break;
   case 3:
-    ebase = RA & ~0xFFF;
+    ebase = val & ~0xFFF;
     break;
 
   case 16:
-    sim->set_tohost(RA);
+    sim->set_tohost(val);
     break;
 }
diff --git a/riscv/processor.cc b/riscv/processor.cc
index 7ca015d..e818840 100644
--- a/riscv/processor.cc
+++ b/riscv/processor.cc
@@ -18,7 +18,7 @@ processor_t::processor_t(sim_t* _sim, char* _mem, size_t _memsz)
   ebase = 0;
   epc = 0;
   badvaddr = 0;
-  set_sr(SR_S);
+  set_sr(SR_S | (support_64bit ? SR_KX : 0));
   set_fsr(0);
 
   memset(counters,0,sizeof(counters));
@@ -40,10 +40,9 @@ void processor_t::init(uint32_t _id)
 void processor_t::set_sr(uint32_t val)
 {
   sr = val & ~SR_ZERO;
-  if(support_64bit)
-    sr |= SR_KX;
-  else
+  if(!support_64bit)
     sr &= ~(SR_KX | SR_UX);
+printf("kx,ux now %d,%d %llx\n",!!(sr & SR_KX),!!(sr & SR_UX),pc);
 
   gprlen = ((sr & SR_S) ? (sr & SR_KX) : (sr & SR_UX)) ? 64 : 32;
 }
@@ -79,15 +78,18 @@ void processor_t::step(size_t n, bool noisy)
   catch(trap_t t)
   {
     i++;
-    take_trap(t);
+    take_trap(t,noisy);
   }
 }
 
-void processor_t::take_trap(trap_t t)
+void processor_t::take_trap(trap_t t, bool noisy)
 {
   demand(t < NUM_TRAPS, "internal error: bad trap number %d", int(t));
   demand(sr & SR_ET, "error mode on core %d!\ntrap %s, pc 0x%016llx",
          id, trap_name(t), (unsigned long long)pc);
+  if(noisy)
+    printf("core %3d: trap %s, pc 0x%016llx\n",
+           id, trap_name(t), (unsigned long long)pc);
 
   set_sr((((sr & ~SR_ET) | SR_S) & ~SR_PS) | ((sr & SR_S) ? SR_PS : 0));
   epc = pc;
diff --git a/riscv/processor.h b/riscv/processor.h
index 8c64d6d..f2024ff 100644
--- a/riscv/processor.h
+++ b/riscv/processor.h
@@ -39,7 +39,7 @@ private:
   // functions
   void set_sr(uint32_t val);
   void set_fsr(uint32_t val);
-  void take_trap(trap_t t);
+  void take_trap(trap_t t, bool noisy);
   void disasm(insn_t insn, reg_t pc);
 
   friend class sim_t;