From: Luke Kenneth Casson Leighton Date: Sat, 9 Mar 2019 09:54:03 +0000 (+0000) Subject: connect corrections to pack with combinatorial logic X-Git-Tag: ls180-24jan2020~1712 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f067330d9c1686e114a93480c3ffb781aac6d6a6;p=ieee754fpu.git connect corrections to pack with combinatorial logic --- diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py index c4d02e74..0bfa9d6f 100644 --- a/src/add/nmigen_add_experiment.py +++ b/src/add/nmigen_add_experiment.py @@ -911,24 +911,32 @@ class FPNormToPack(FPState, FPID): self.r_out_z = FPNumBase(width) self.cmod = FPCorrectionsMod(width) + self.c_out_z = FPNumBase(width) + + self.pmod = FPPackMod(width) self.out_z = FPNumBase(width) def setup(self, m, in_z, in_of, in_mid): """ links module to inputs and outputs """ self.mod.setup(m, in_z, in_of, self.n_out_z) + self.rmod.setup(m, self.n_out_z, self.n_out_roundz) m.d.comb += self.n_out_roundz.eq(self.mod.out_of.roundz) m.d.comb += self.r_out_z.copy(self.rmod.out_z) + self.cmod.setup(m, self.r_out_z) + m.d.comb += self.c_out_z.copy(self.cmod.out_z) + + self.pmod.setup(m, self.c_out_z) if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) def action(self, m): self.idsync(m) - m.next = "pack" - m.d.sync += self.out_z.copy(self.cmod.out_z) + m.d.sync += self.out_z.v.eq(self.pmod.out_z.v) + m.next = "pack_put_z" class FPRoundMod: @@ -1025,6 +1033,12 @@ class FPPackMod: self.in_z = FPNumOut(width, False) self.out_z = FPNumOut(width, False) + def setup(self, m, in_z): + """ links module to inputs and outputs + """ + m.submodules.pack = self + m.d.comb += self.in_z.copy(in_z) + def elaborate(self, platform): m = Module() m.submodules.pack_in_z = self.in_z @@ -1046,8 +1060,7 @@ class FPPack(FPState, FPID): def setup(self, m, in_z, in_mid): """ links module to inputs and outputs """ - m.submodules.pack = self.mod - m.d.comb += self.mod.in_z.copy(in_z) + self.mod.setup(m, in_z) if self.in_mid is not None: m.d.comb += self.in_mid.eq(in_mid) @@ -1203,14 +1216,11 @@ class FPADDBaseMod(FPID): n1 = self.add_state(FPNormToPack(self.width, self.id_wid)) n1.setup(m, add1.out_z, add1.out_of, add0.in_mid) - pa = self.add_state(FPPack(self.width, self.id_wid)) - pa.setup(m, n1.out_z, n1.in_mid) - - ppz = self.add_state(FPPutZ("pack_put_z", pa.out_z, self.out_z, - pa.in_mid, self.out_mid)) + ppz = self.add_state(FPPutZ("pack_put_z", n1.out_z, self.out_z, + n1.in_mid, self.out_mid)) pz = self.add_state(FPPutZ("put_z", sc.out_z, self.out_z, - pa.in_mid, self.out_mid)) + sc.in_mid, self.out_mid)) class FPADDBase(FPState, FPID):