From: Bjoern A. Zeeb Date: Thu, 9 Feb 2017 23:54:28 +0000 (-0500) Subject: arm: AArch64 report cache size correctly when reading CTR_EL0 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0786704db90b0020066d19652886b9311516b45;p=gem5.git arm: AArch64 report cache size correctly when reading CTR_EL0 Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not implmemented. With that an operating system relying on the cache line sizes reported in order to manage the caches would (a) panic given the returned value 0 is not valid (high bit is RES1) or (b) worst case would assume a cache line size of 4 doing a tremendous amount of extra instruction work (including fetching). Return the same values as for ARMv7 as the fields seem to be the same, or RES0/1 seem to be reported accordingly for AArch64 In collaboration with: Andrew Turner Testing Done: Checked on FreeBSD boots with extra printfs; also observed a reduction of a factor of about 10 in instruction fetches for a simple micro-test. Reviewed at http://reviews.gem5.org/r/3667/ Signed-off-by: Jason Lowe-Power --- diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 0db6d433d..c54d7746d 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -594,7 +594,8 @@ ISA::readMiscReg(int misc_reg, ThreadContext *tc) warn_once("The ccsidr register isn't implemented and " "always reads as 0.\n"); break; - case MISCREG_CTR: + case MISCREG_CTR: // AArch32, ARMv7, top bit set + case MISCREG_CTR_EL0: // AArch64 { //all caches have the same line size in gem5 //4 byte words in ARM