From: Rob Clark <robdclark@chromium.org>
Date: Tue, 12 May 2020 23:39:20 +0000 (-0700)
Subject: freedreno/a6xx: fix max-scissor opt
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f079c00ffc1c9e85321955f679e656196f724848;p=mesa.git

freedreno/a6xx: fix max-scissor opt

On a6xx we need a 0,0 based scissor in the binning pass, but can use the
blit-scissor to avoid restore/resolve of untouched pixels, and use the
conditional execution if the IB to bin to skip bins with no geometry
(due to the scissor).

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5021>
---

diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 8dfad67d7c3..1abaef699f5 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -626,14 +626,9 @@ emit_binning_pass(struct fd_batch *batch)
 	const struct fd_gmem_stateobj *gmem = batch->gmem_state;
 	struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
 
-	uint32_t x1 = gmem->minx;
-	uint32_t y1 = gmem->miny;
-	uint32_t x2 = gmem->minx + gmem->width - 1;
-	uint32_t y2 = gmem->miny + gmem->height - 1;
-
 	debug_assert(!batch->tessellation);
 
-	set_scissor(ring, x1, y1, x2, y2);
+	set_scissor(ring, 0, 0, gmem->width - 1, gmem->height - 1);
 
 	emit_marker6(ring, 7);
 	OUT_PKT7(ring, CP_SET_MARKER, 1);
@@ -929,13 +924,12 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
 static void
 set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
 {
-	struct pipe_scissor_state blit_scissor;
-	struct pipe_framebuffer_state *pfb = &batch->framebuffer;
+	struct pipe_scissor_state blit_scissor = batch->max_scissor;
 
-	blit_scissor.minx = 0;
-	blit_scissor.miny = 0;
-	blit_scissor.maxx = align(pfb->width, batch->ctx->screen->gmem_alignw);
-	blit_scissor.maxy = align(pfb->height, batch->ctx->screen->gmem_alignh);
+	blit_scissor.minx = ROUND_DOWN_TO(blit_scissor.minx, 16);
+	blit_scissor.miny = ROUND_DOWN_TO(blit_scissor.miny, 4);
+	blit_scissor.maxx = ALIGN(blit_scissor.maxx, 16);
+	blit_scissor.maxy = ALIGN(blit_scissor.maxy, 4);
 
 	OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
 	OUT_RING(ring,
diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c
index 73db133ae4a..bbffda66e47 100644
--- a/src/gallium/drivers/freedreno/freedreno_gmem.c
+++ b/src/gallium/drivers/freedreno/freedreno_gmem.c
@@ -460,7 +460,10 @@ gmem_key_init(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
 		key->cbuf_cpp[i] *= pfb->samples;
 	}
 
-	if ((fd_mesa_debug & FD_DBG_NOSCIS) || no_scis_opt) {
+	/* NOTE: on a6xx, the max-scissor-rect is handled in fd6_gmem, and
+	 * we just rely on CP_COND_EXEC to skip bins with no geometry.
+	 */
+	if ((fd_mesa_debug & FD_DBG_NOSCIS) || no_scis_opt || is_a6xx(screen)) {
 		key->minx = 0;
 		key->miny = 0;
 		key->width = pfb->width;