From: Clifford Wolf <clifford@clifford.at>
Date: Mon, 15 Aug 2016 06:26:20 +0000 (+0200)
Subject: Fixed upto handling in verilog back-end
X-Git-Tag: yosys-0.7~142
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0a8713fea9fea016e5a83fefd9e00a32f4a88d2;p=yosys.git

Fixed upto handling in verilog back-end
---

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index caa668c33..705d74aa1 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -141,6 +141,9 @@ bool is_reg_wire(RTLIL::SigSpec sig, std::string &reg_name)
 	if (sig.size() != chunk.wire->width) {
 		if (sig.size() == 1)
 			reg_name += stringf("[%d]", chunk.wire->start_offset +  chunk.offset);
+		else if (chunk.wire->upto)
+			reg_name += stringf("[%d:%d]", (chunk.wire->width - (chunk.offset + chunk.width - 1) - 1) + chunk.wire->start_offset,
+					(chunk.wire->width - chunk.offset - 1) + chunk.wire->start_offset);
 		else
 			reg_name += stringf("[%d:%d]", chunk.wire->start_offset +  chunk.offset + chunk.width - 1,
 					chunk.wire->start_offset +  chunk.offset);