From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 6 Jul 2020 10:26:24 +0000 (+0200)
Subject: interconnect/csr_bus: move/rewrite paged access warning.
X-Git-Tag: 24jan2021_ls180~106
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0a97791a90bbb6b5bb4497aa33ba1c5fa2bad73;p=litex.git

interconnect/csr_bus: move/rewrite paged access warning.

Was incorrectly triggered with csr_data_width=32.
---

diff --git a/litex/soc/interconnect/csr_bus.py b/litex/soc/interconnect/csr_bus.py
index ac8d0638..b91a458e 100644
--- a/litex/soc/interconnect/csr_bus.py
+++ b/litex/soc/interconnect/csr_bus.py
@@ -95,14 +95,12 @@ class SRAM(Module):
         else:
             mem = Memory(data_width, mem_or_size//(data_width//8), init=init)
         mem_size = int(mem.width*mem.depth/8)
-        if mem_size > aligned_paging:
-            print("WARNING: memory > {} bytes in CSR region requires paged access (mem_size = {} bytes)".format(
-                aligned_paging, mem_size))
         csrw_per_memw = (mem.width + data_width - 1)//data_width
         word_bits = log2_int(csrw_per_memw)
         page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
         if page_bits:
             self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
+            printf("WARNING: SRAM CSR memory will requires paged access.")
         else:
             self._page = None
         if read_only is None: