From: Victor Do Nascimento <victor.donascimento@arm.com>
Date: Mon, 30 Oct 2023 12:39:28 +0000 (+0000)
Subject: aarch64: Add arch support for LSE128 extension
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0d70d8ee63b6f6a59cf4a10268f546b0bc80777;p=binutils-gdb.git

aarch64: Add arch support for LSE128 extension

Enable the `+lse128' feature modifier which, together with new
internal feature flags, enables LSE128 instructions, which are
represented via the new `_LSE128_INSN' macro.

gas/ChangeLog:

	* config/tc-aarch64.c (aarch64_features): Add new "lse128"
	entry.

include/ChangeLog:

	* include/opcode/aarch64.h (enum aarch64_feature_bit): New
	AARCH64_FEATURE_LSE128 feature bit.
	(enum aarch64_insn_class): New lse128_atomic instruction class.

opcodes/ChangeLog:

	* opcodes/aarch64-tbl.h (aarch64_feature_lse128): New.
	(LSE128): Likewise.
	(_LSE128_INSN): Likewise.
---

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 4367455aa23..70c0ed652a5 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10239,6 +10239,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
 			AARCH64_FEATURE (SIMD)},
   {"fp",		AARCH64_FEATURE (FP), AARCH64_NO_FEATURES},
   {"lse",		AARCH64_FEATURE (LSE), AARCH64_NO_FEATURES},
+  {"lse128",		AARCH64_FEATURES (2, LSE, LSE128), AARCH64_NO_FEATURES},
   {"simd",		AARCH64_FEATURE (SIMD), AARCH64_FEATURE (FP)},
   {"pan",		AARCH64_FEATURE (PAN), AARCH64_NO_FEATURES},
   {"lor",		AARCH64_FEATURE (LOR), AARCH64_NO_FEATURES},
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 8af38f27320..81c18181831 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -265,6 +265,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Guarded Control Stack Extension.
 @item @code{the} @tab ARMv8-A/Armv9-A @tab ARMv8.9-A/Armv9.4-A or later
  @tab Enable Translation Hardening extension.
+@item @code{lse128} @tab Armv9.4-A @tab No
+ @tab Enable the 128-bit Atomic Instructions extension.  This implies @code{lse}.
 
 @end multitable
 
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 1ede57094f8..6be2885c78f 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -167,6 +167,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME2,
   /* Translation Hardening Extension.  */
   AARCH64_FEATURE_THE,
+  /* LSE128.  */
+  AARCH64_FEATURE_LSE128,
   AARCH64_NUM_FEATURES
 };
 
@@ -857,6 +859,7 @@ enum aarch64_insn_class
   log_imm,
   log_shift,
   lse_atomic,
+  lse128_atomic,
   movewide,
   pcreladdr,
   ic_system,
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index bc385427016..752972a3d06 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2470,6 +2470,8 @@ static const aarch64_feature_set aarch64_feature_crc =
   AARCH64_FEATURE (CRC);
 static const aarch64_feature_set aarch64_feature_lse =
   AARCH64_FEATURE (LSE);
+static const aarch64_feature_set aarch64_feature_lse128 =
+  AARCH64_FEATURES (2, LSE, LSE128);
 static const aarch64_feature_set aarch64_feature_lor =
   AARCH64_FEATURE (LOR);
 static const aarch64_feature_set aarch64_feature_rdma =
@@ -2584,6 +2586,7 @@ static const aarch64_feature_set aarch64_feature_the =
 #define SIMD		&aarch64_feature_simd
 #define CRC		&aarch64_feature_crc
 #define LSE		&aarch64_feature_lse
+#define LSE128		&aarch64_feature_lse128
 #define LOR		&aarch64_feature_lor
 #define RDMA		&aarch64_feature_rdma
 #define FP_F16		&aarch64_feature_fp_f16
@@ -2652,6 +2655,8 @@ static const aarch64_feature_set aarch64_feature_the =
   { NAME, OPCODE, MASK, CLASS, 0, CRC, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LSE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, LSE, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define _LSE128_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, LSE128, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LOR_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, LOR, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define RDMA_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \