From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 26 Apr 2017 14:09:32 +0000 (+0200)
Subject: Add support for `resetall compiler directive
X-Git-Tag: yosys-0.8~445
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0db8ffdbcd64560739639dfde078c14f9939604;p=yosys.git

Add support for `resetall compiler directive
---

diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index 41b5eac19..cf220fef9 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -438,6 +438,13 @@ std::string frontend_verilog_preproc(std::istream &f, std::string filename, cons
 			continue;
 		}
 
+		if (tok == "`resetall") {
+			defines_map.clear();
+			defines_with_args.clear();
+			global_defines_cache.clear();
+			continue;
+		}
+
 		if (tok.size() > 1 && tok[0] == '`' && defines_map.count(tok.substr(1)) > 0) {
 			std::string name = tok.substr(1);
 			// printf("expand: >>%s<< -> >>%s<<\n", name.c_str(), defines_map[name].c_str());