From: lkcl <lkcl@web>
Date: Sat, 7 May 2022 11:31:20 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~2337
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0ea2971cafd84d2db91a24b25cce12da41241b8;p=libreriscv.git

---

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index a93d29390..f27479779 100644
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -257,7 +257,11 @@ Vector instructions in RISC-V as there are in the RV64GC Scalar base.
 The question then becomes: with all the duplication of arithmetic
 operations just to make the registers scalar or vector, why not
 leverage the *existing* Scalar ISA with some sort of "context"
-or prefix that augments its behaviour?  Then, the Instruction Decode
+or prefix that augments its behaviour? Make "Scalar instruction"
+synonymous with "Scalar instruction" and through contextual
+augmentation the Scalar ISA *becomes* the Vector ISA.
+Then, by not having to have any Vector instructions at all,
+the Instruction Decode
 phase is greatly simplified, reducing design complexity and leaving
 plenty of headroom for further expansion.