From: Eddie Hung <eddieh@ece.ubc.ca>
Date: Wed, 13 Feb 2019 22:09:36 +0000 (-0800)
Subject: Merge remote-tracking branch 'origin/read_aiger' into xaig
X-Git-Tag: working-ls180~1237^2~340
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f0f5d8a5cc44c8b89d234ab9cac20f294a821271;p=yosys.git

Merge remote-tracking branch 'origin/read_aiger' into xaig
---

f0f5d8a5cc44c8b89d234ab9cac20f294a821271
diff --cc frontends/aiger/aigerparse.cc
index cc4abe184,7df28fe87..56bffcf38
--- a/frontends/aiger/aigerparse.cc
+++ b/frontends/aiger/aigerparse.cc
@@@ -414,19 -229,12 +412,14 @@@ void AigerReader::parse_aiger_ascii(boo
              log_error("Line %u cannot be interpreted as an AND!\n", line_count);
  
          log_debug("%d %d %d is an AND\n", l1, l2, l3);
 -        log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
 -        RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 -        RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 -        RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
 -        module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
 +        if (create_and) {
 +            log_assert(!(l1 & 1));
 +            RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
 +            RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
 +            RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
- 
-             RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
-             and_cell->setPort("\\A", i1_wire);
-             and_cell->setPort("\\B", i2_wire);
-             and_cell->setPort("\\Y", o_wire);
++            module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
 +        }
      }
-     std::getline(f, line); // Ignore up to start of next line
  }
  
  static unsigned parse_next_delta_literal(std::istream &f, unsigned ref)