From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Apr 2015 12:37:39 +0000 (+0200)
Subject: liteusb: pep8 (E265)
X-Git-Tag: 24jan2021_ls180~2343
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f10e87306341097b1c9142071dcfcade3c4b3f73;p=litex.git

liteusb: pep8 (E265)
---

diff --git a/misoclib/com/liteusb/core/crc.py b/misoclib/com/liteusb/core/crc.py
index 95e9db8c..83aab313 100644
--- a/misoclib/com/liteusb/core/crc.py
+++ b/misoclib/com/liteusb/core/crc.py
@@ -38,7 +38,7 @@ class CRCEngine(Module):
         self.last = Signal(width)
         self.next = Signal(width)
 
-        ###
+        # # #
 
         def _optimize_eq(l):
             """
@@ -108,7 +108,7 @@ class CRC32(Module):
         self.value = Signal(self.width)
         self.error = Signal()
 
-        ###
+        # # #
 
         self.submodules.engine = CRCEngine(dat_width, self.width, self.polynom)
         reg = Signal(self.width, reset=self.init)
@@ -144,7 +144,7 @@ class CRCInserter(Module):
         self.source = source = Source(layout)
         self.busy = Signal()
 
-        ###
+        # # #
 
         dw = flen(sink.d)
         crc = crc_class(dw)
@@ -225,7 +225,7 @@ class CRCChecker(Module):
         self.source = source = Source(layout)
         self.busy = Signal()
 
-        ###
+        # # #
 
         dw = flen(sink.d)
         crc = crc_class(dw)
diff --git a/misoclib/com/liteusb/frontend/uart.py b/misoclib/com/liteusb/frontend/uart.py
index a03e67eb..1147fa68 100644
--- a/misoclib/com/liteusb/frontend/uart.py
+++ b/misoclib/com/liteusb/frontend/uart.py
@@ -20,7 +20,7 @@ class LiteUSBUART(Module, AutoCSR):
         self.source = source = Source(user_layout)
         self.sink = sink = Sink(user_layout)
 
-        ###
+        # # #
 
         # TX
         tx_start = self._rxtx.re
diff --git a/misoclib/com/liteusb/phy/ft2232h.py b/misoclib/com/liteusb/phy/ft2232h.py
index cc5b4005..d8e70dd6 100644
--- a/misoclib/com/liteusb/phy/ft2232h.py
+++ b/misoclib/com/liteusb/phy/ft2232h.py
@@ -304,11 +304,10 @@ def main():
     tb = TB()
     run_simulation(tb, ncycles=8000, vcd_name="tb_phy.vcd")
 
-    ###
-    #print(tb.user.rd_data)
-    #print(tb.model.wr_data)
-    #print(len(tb.user.rd_data))
-    #print(len(tb.model.wr_data))
+    # print(tb.user.rd_data)
+    # print(tb.model.wr_data)
+    # print(len(tb.user.rd_data))
+    # print(len(tb.model.wr_data))
 
     print_results("F2232HModel --> UserModel", model_rd_data, tb.user.rd_data)
     print_results("UserModel --> FT2232HModel", user_wr_data,  tb.model.wr_data)