From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 22 May 2019 19:43:35 +0000 (+0100)
Subject: invert write pending before use
X-Git-Tag: div_pipeline~1984
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f115426371727c0ef5222a8877b2f99c35d1c703;hp=933a474a77a96e6a0cf8a0e05b33d17820ded4de;p=soc.git

invert write pending before use
---

diff --git a/src/scoreboard/fn_unit.py b/src/scoreboard/fn_unit.py
index 886c8cf2..a0d31715 100644
--- a/src/scoreboard/fn_unit.py
+++ b/src/scoreboard/fn_unit.py
@@ -163,7 +163,7 @@ class FnUnit(Elaboratable):
         # readable output signal
         g_rd = Signal(self.reg_width, reset_less=True)
         ro = Signal(reset_less=True)
-        m.d.comb += g_rd.eq(self.g_wr_pend_i & self.rd_pend_o)
+        m.d.comb += g_rd.eq(~self.g_wr_pend_i & self.rd_pend_o)
         m.d.comb += ro.eq(~g_rd.bool())
         m.d.comb += self.readable_o.eq(ro)