From: whitequark <cz@m-labs.hk>
Date: Sat, 15 Dec 2018 14:20:10 +0000 (+0000)
Subject: Move star imports to make `from nmigen import *` usable.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f11d8dc69c60d986d22e5ffe4021bacb6a7fd024;p=nmigen.git

Move star imports to make `from nmigen import *` usable.
---

diff --git a/examples/alu.py b/examples/alu.py
index 456a75b..4b051c6 100644
--- a/examples/alu.py
+++ b/examples/alu.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 
diff --git a/examples/alu_hier.py b/examples/alu_hier.py
index 6f862ca..8551d38 100644
--- a/examples/alu_hier.py
+++ b/examples/alu_hier.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 
diff --git a/examples/arst.py b/examples/arst.py
index c35640e..e99fc8d 100644
--- a/examples/arst.py
+++ b/examples/arst.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 
diff --git a/examples/cdc.py b/examples/cdc.py
index 8bbdc11..7d2486d 100644
--- a/examples/cdc.py
+++ b/examples/cdc.py
@@ -1,6 +1,5 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
-from nmigen.genlib.cdc import *
 
 
 i, o = Signal(name="i"), Signal(name="o")
diff --git a/examples/clkdiv.py b/examples/clkdiv.py
index ce49eae..7be26b6 100644
--- a/examples/clkdiv.py
+++ b/examples/clkdiv.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog, pysim
 
 
diff --git a/examples/ctrl.py b/examples/ctrl.py
index 64c3b5d..fa9cf44 100644
--- a/examples/ctrl.py
+++ b/examples/ctrl.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog, pysim
 
 
diff --git a/examples/pmux.py b/examples/pmux.py
index cda5447..27ec33f 100644
--- a/examples/pmux.py
+++ b/examples/pmux.py
@@ -1,4 +1,4 @@
-from nmigen.fhdl import *
+from nmigen import *
 from nmigen.back import rtlil, verilog
 
 
diff --git a/nmigen/__init__.py b/nmigen/__init__.py
index e69de29..36b1791 100644
--- a/nmigen/__init__.py
+++ b/nmigen/__init__.py
@@ -0,0 +1,7 @@
+from .fhdl.ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
+from .fhdl.dsl import Module
+from .fhdl.cd import ClockDomain
+from .fhdl.ir import Fragment
+from .fhdl.xfrm import ResetInserter, CEInserter
+
+from .genlib.cdc import MultiReg
diff --git a/nmigen/fhdl/__init__.py b/nmigen/fhdl/__init__.py
index cc83fb5..e69de29 100644
--- a/nmigen/fhdl/__init__.py
+++ b/nmigen/fhdl/__init__.py
@@ -1,5 +0,0 @@
-from .cd import ClockDomain
-from .ast import Value, Const, Mux, Cat, Repl, Signal, ClockSignal, ResetSignal
-from .ir import Fragment
-from .dsl import Module
-from .xfrm import ResetInserter, CEInserter