From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 10 Jul 2020 09:16:28 +0000 (+0100)
Subject: add debugging chain for #425
X-Git-Tag: div_pipeline~112
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f11ffd6b4be87763d7b93a77215212e1004f76e3;p=soc.git

add debugging chain for #425
---

diff --git a/src/soc/fu/div/pipeline.py b/src/soc/fu/div/pipeline.py
index d72083e5..801cd44a 100644
--- a/src/soc/fu/div/pipeline.py
+++ b/src/soc/fu/div/pipeline.py
@@ -34,6 +34,7 @@ class DivStagesEnd(PipeModBaseChain):
         core_final = DivCoreFinalStage(self.pspec)
         div_out = DivOutputStage(self.pspec)
         alu_out = DivMulOutputStage(self.pspec)
+        self.div_out = div_out # debugging - bug #425
         return [core_final, div_out, alu_out]
 
 
diff --git a/src/soc/fu/div/test/test_pipe_caller.py b/src/soc/fu/div/test/test_pipe_caller.py
index 6b80fcc1..403c0b57 100644
--- a/src/soc/fu/div/test/test_pipe_caller.py
+++ b/src/soc/fu/div/test/test_pipe_caller.py
@@ -217,6 +217,7 @@ class TestRunner(FHDLTestCase):
                     while not vld:
                         yield
                         vld = yield alu.n.valid_o
+                        print ("bug track", alu.pipe_end.div_out)
                     yield
 
                     yield from self.check_alu_outputs(alu, pdecode2, sim, code)