From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 5 Aug 2020 15:22:08 +0000 (+0000)
Subject: find semi-suitable width for spr0, add missing int dmi signals
X-Git-Tag: partial-core-ls180-gdsii~91^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f12666dee5a09b4677632f5110d311b9e2ee0da9;p=soclayout.git

find semi-suitable width for spr0, add missing int dmi signals
---

diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py
index bd0d61c..f9ae7c9 100644
--- a/experiments9/doDesign.py
+++ b/experiments9/doDesign.py
@@ -464,17 +464,17 @@ def scriptMain ( **kw ):
             , (IE | AE  , 'xer_so_ok'                    , 0, l(20),  1)
             , (IE | AE  , 'cu_rd_rel_o({})'              , 0,     0,  6)
             , (IE | AE  , 'cu_wr_rel_o({})'              , 0,     0,  6)
-            , (IN | AE  , 'dest5_o({})'                  , 0,     0,  2)
-            , (IN | AE  , 'dest6_o({})'                  , 0,     0,  2)
+            , (IE | AE  , 'dest5_o({})'                  , 0,     0,  2)
+            , (IE | AE  , 'dest6_o({})'                  , 0,     0,  2)
             , (IE | AE  , 'dest3_o({})'                  , 0, l(20), 64)
-            , (IE | AE  , 'dest2_o({})'                  , 0, l(20), 64)
-            , (IE | AE  , 'dest1_o({})'                  , 0, l(20), 64)
+            , (IS | AE  , 'dest2_o({})'                  , 0, l(20), 64)
+            , (IS | AE  , 'dest1_o({})'                  , 0, l(20), 64)
                      ]
             )
         blockSpr0.state.cfg.etesian.uniformDensity = True
         blockSpr0.state.cfg.etesian.spaceMargin    = 0.5
         blockSpr0.state.cfg.katana.searchHalo      = 1
-        blockSpr0.state.fixedHeight = l(4500)
+        blockSpr0.state.fixedHeight = l(2200)
         blockSpr0.state.useSpares   = False
        #rvalue = blockSpr0.build()
 
@@ -559,13 +559,15 @@ def scriptMain ( **kw ):
             ( cellInt
             , ioPins=[ (IN              , 'coresync_clk'    , l(805.0) )
                      , (IW | AB, 'coresync_rst'    , 0, l(20),  1)
-                     , (IW | AB, 'wen({})'         , 0, l(20), 32)
-                     , (IW | AB, 'wen_1({})'       , 0, l(20), 32)
-                     , (IW | AB, 'src1_ren({})'    , 0, l(20), 32)
-                     , (IW | AB, 'src2_ren({})'    , 0, l(20), 32)
-                     , (IW | AB, 'src3_ren({})'    , 0, l(20), 32)
-                     , (IS | AB, 'data_i({})'      , 0, l(20), 64)
-                     , (IS | AB, 'data_i_2({})'    , 0, l(20), 64)
+                     , (IN | AB, 'wen({})'         , 0, l(20), 32)
+                     , (IN | AB, 'wen_1({})'       , 0, l(20), 32)
+                     , (IN | AB, 'dmi_ren({})'    , 0, l(20), 32)
+                     , (IN | AB, 'src1_ren({})'    , 0, l(20), 32)
+                     , (IN | AB, 'src2_ren({})'    , 0, l(20), 32)
+                     , (IN | AB, 'src3_ren({})'    , 0, l(20), 32)
+                     , (IN | AB, 'data_i({})'      , 0, l(20), 64)
+                     , (IN | AB, 'data_i_2({})'    , 0, l(20), 64)
+                     , (IN | AE  , 'dmi_data_o({})' , 0, l(10), 64)
                      , (IN | AE  , 'src1_data_o({})' , 0, l(10), 64)
                      , (IN | AE  , 'src2_data_o({})' , 0, l(10), 64)
                      , (IN | AE  , 'src3_data_o({})' , 0, l(10), 64)