From: Luke Kenneth Casson Leighton Date: Fri, 27 Jul 2018 07:46:31 +0000 (+0100) Subject: add quart wrapper X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1467456975ff061ce705a023728a72adab41ec0;p=shakti-peripherals.git add quart wrapper --- diff --git a/src/peripherals/uart/Makefile b/src/peripherals/uart/Makefile new file mode 100644 index 0000000..931878c --- /dev/null +++ b/src/peripherals/uart/Makefile @@ -0,0 +1,45 @@ +### Makefile for the cclass project + +TOP_MODULE:=mkQUART +TOP_FILE:=quart.bsv +TOP_DIR:=./ +WORKING_DIR := $(shell pwd) + +BSVINCDIR:= .:%/Prelude:%/Libraries:%/Libraries/BlueNoC: +BSVINCDIR:= $(BSVINCDIR):../../core +BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4 +BSVINCDIR:= $(BSVINCDIR):../../uncore/axi4lite +BSVINCDIR:= $(BSVINCDIR):./test + +default: gen_verilog + +check-blue: + @if test -z "$$BLUESPECDIR"; then echo "BLUESPECDIR variable not set"; exit 1; fi; + +###### Setting the variables for bluespec compile #$############################ +BSVCOMPILEOPTS:= -check-assert -suppress-warnings G0020 -keep-fires -opt-undetermined-vals -remove-false-rules -remove-empty-rules -remove-starved-rules +BSVLINKOPTS:=-parallel-sim-link 8 -keep-fires +VERILOGDIR:=./verilog/ +BSVBUILDDIR:=./bsv_build/ +BSVOUTDIR:=./bin +################################################################################ + +########## BSIM COMPILE, LINK AND SIMULATE TARGETS ########################## +.PHONY: check-restore +check-restore: + @if [ "$(define_macros)" != "$(old_define_macros)" ]; then make clean ; fi; + +.PHONY: gen_verilog +gen_verilog: check-restore check-blue + @echo Compiling mkTbSoc in Verilog for simulations ... + @mkdir -p $(BSVBUILDDIR); + @mkdir -p $(VERILOGDIR); + bsc -u -verilog -elab -vdir $(VERILOGDIR) -bdir $(BSVBUILDDIR) -info-dir $(BSVBUILDDIR) $(define_macros) -D verilog=True $(BSVCOMPILEOPTS) -verilog-filter ${BLUESPECDIR}/bin/basicinout -p $(BSVINCDIR) -g $(TOP_MODULE) $(TOP_DIR)/$(TOP_FILE) 2>&1 | tee bsv_compile.log + @echo Compilation finished + +############################################################################# + +.PHONY: clean +clean: + rm -rf $(BSVBUILDDIR) *.log $(BSVOUTDIR) ./bbl* + rm -rf verilog obj_dir bsv_src diff --git a/src/peripherals/uart/quart.bsv b/src/peripherals/uart/quart.bsv index 56a0965..2dc6c7e 100644 --- a/src/peripherals/uart/quart.bsv +++ b/src/peripherals/uart/quart.bsv @@ -29,84 +29,84 @@ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -------------------------------------------------------------------- */ -package spi; +package quart; import AXI4_Lite_Types :: *; import AXI4_Lite_Fabric :: *; import GetPut::*; - import qspi::*; + import Uart16550::*; `include "instance_defines.bsv" - (*always_ready, always_enabled*) - interface SPI_out; - interface Get#(Bit#(1)) clk_o; - method Bit#(9) io0_sdio_ctrl; - method Bit#(9) io1_sdio_ctrl; - // index 0 is MOSI, index 1 is MISO. - interface Get#(Bit#(2)) io_out; - interface Get#(Bit#(2)) io_out_en; - interface Put#(Bit#(2)) io_in; - interface Get#(Bit#(1)) ncs_o; + interface QUART_out; + interface Put#(Bit#(1)) srx_in; + interface Put#(Bit#(1)) cts_in; + interface Get#(Bit#(1)) stx_out; + interface Get#(Bit#(1)) rts_out; endinterface - interface Ifc_spi; - interface SPI_out out; + interface QUART_AXI4_Lite_Ifc; + interface QUART_out out; interface AXI4_Lite_Slave_IFC#(`PADDR,`Reg_width,`USERSPACE) slave; - // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5 = request_ready - method Bit#(6) interrupts; + (* always_ready, always_enabled *) method Bit#(1) irq; endinterface - (*synthesize*) - module mkspi(Ifc_spi); - - Ifc_qspi qspi <- mkqspi(); - - interface out = interface SPI_out - method Bit#(9) io0_sdio_ctrl; - return qspi.out.io0_sdio_ctrl; - endmethod - method Bit#(9) io1_sdio_ctrl; - return qspi.out.io1_sdio_ctrl; - endmethod - interface io_out = interface Get - method ActionValue#(Bit#(2)) get; - let temp2 <- qspi.out.io_out.get; - Bit#(2) temp; - temp[0] = temp2[0]; - temp[1] = temp2[1]; + module mkQUART#(Clock core_clock, Reset core_reset) + (QUART_AXI4_Lite_Ifc); + + Uart16550_AXI4_Lite_Ifc uart <- mkUart16550(core_clock, core_reset); + //uart.pin_dsr_sync <= in; + //uart.pin_ri_sync <= in; + //uart.pin_dcd_sync <= in; + Bit#(1) v1 = 1; + Bit#(1) v0 = 1; + let dsr_in = uart.coe_rs232.dsr_in.put; + dsr_in = v1; + let dcd_in = uart.coe_rs232.dcd_in.put; + dcd_in = v1; + let ri_in = uart.coe_rs232.ri_in.put; + ri_in = v0; + + let temp2 <- uart.coe_rs232.dtr_out.get; + Bit#(1) temp = temp2; + uart.coe_rs232.dtr_out.get(temp); + + interface out = interface QUART_out + interface srx_in = interface Put + method Action put(Bit#(1) in); + uart.coe_rs232.srx_in.put(in); // RX Input + endmethod + endinterface; + + interface cts_in = interface Put + method Action put(Bit#(1) in); + uart.coe_rs232.cts_in.put(in); // CTS Input + endmethod + endinterface; + + interface stx_out = interface Get + method ActionValue#(Bit#(1)) get; + let temp2 <- uart.coe_rs232.stx_out.get; + Bit#(1) temp = temp2; return temp; - endmethod - endinterface; - interface io_out_en = interface Get - method ActionValue#(Bit#(2)) get; - let temp2 <- qspi.out.io_out_en.get; - Bit#(2) temp; - temp[0] = temp2[0]; - temp[1] = temp2[1]; + endmethod + endinterface; + + interface rts_out = interface Get + method ActionValue#(Bit#(1)) get; + let temp2 <- uart.coe_rs232.rts_out.get; + Bit#(1) temp = temp2; return temp; - endmethod - endinterface; - interface io_in = interface Put - method Action put(Bit#(2) in); - Bit#(4) temp; - temp[3] = 0; - temp[2] = 0; - temp[1] = in[1]; - temp[0] = in[0]; - qspi.out.io_in.put(temp); - endmethod - endinterface; - interface clk_o = qspi.out.clk_o; - interface ncs_o = qspi.out.ncs_o; + endmethod + endinterface; + endinterface; - interface slave = qspi.slave; + interface slave = uart.slave_axi_uart; - // 0=TOF, 1=SMF, 2=Threshold, 3=TCF, 4=TEF 5=request_ready - method Bit#(6) interrupts; - return qspi.interrupts; + method Bit#(1) irq; + return uart.irq; endmethod endmodule diff --git a/src/peripherals/uart/test/instance_defines.bsv b/src/peripherals/uart/test/instance_defines.bsv new file mode 100644 index 0000000..38780f5 --- /dev/null +++ b/src/peripherals/uart/test/instance_defines.bsv @@ -0,0 +1,24 @@ +`define ADDR 32 +`define PADDR 32 +`define DATA 64 +`define Reg_width 64 +`define USERSPACE 0 + +// TODO: work out if these are needed +`define PWM_AXI4Lite +`define PRFDEPTH 6 +`define VADDR 39 +`define DCACHE_BLOCK_SIZE 4 +`define DCACHE_WORD_SIZE 8 +`define PERFMONITORS 64 +`define DCACHE_WAYS 4 +`define DCACHE_TAG_BITS 20 // tag_bits = 52 +`define PLIC + `define PLICBase 'h0c000000 + `define PLICEnd 'h10000000 +`define INTERRUPT_PINS 64 + +`define BAUD_RATE 130 +`ifdef simulate + `define BAUD_RATE 5 //130 // +`endif