From: lkcl <lkcl@web>
Date: Sat, 9 Jul 2022 12:40:38 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1229
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f14a469c44fda74f90a50dca5e8626beaef8fd5c;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index f3ebe2f47..5f530d118 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -123,10 +123,9 @@ SVP64 "Modes":
 Core SVP64 instructions:
 
 * [[sv/setvl]] the Cray-style "Vector Length" instruction
-* [[sv/remap]] "Remapping" for Matrix Multiply, DCT/FFT
-  and RGB-style "Structure Packing"
-  as well as Indexing. Describes svindex, svremap and svshape and
-  associated SPRs.
+* svremap, svindex and svshape: part of [[sv/remap]] "Remapping" for
+  Matrix Multiply, DCT/FFT and RGB-style "Structure Packing"
+  as well as Indexing. Also describes associated SPRs.
 * [[sv/svstep]] Key stepping instruction, primarily for
   Vertical-First Mode and also providing traditional "Vector Iota"
   capability.