From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 18 May 2021 11:49:45 +0000 (+0100)
Subject: revert register reordering in ISACaller
X-Git-Tag: xlen-bcd~600
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f15a2fce4b13e44cc52c144c0f3a16943c63e9b4;p=openpower-isa.git

revert register reordering in ISACaller
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 2efb0ea2..28400e64 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -52,6 +52,8 @@ special_sprs = {
 
 
 REG_SORT_ORDER = {
+    # TODO (lkcl): adjust other registers that should be in a particular order
+    # probably CA, CA32, and CR
     "FRT": 0,
     "FRA": 0,
     "FRB": 0,
@@ -62,16 +64,15 @@ REG_SORT_ORDER = {
     "RB": 0,
     "RC": 0,
     "RS": 0,
-
-    "LR": 1,
-    "CTR": 1,
-    "TAR": 1,
-    "MSR": 1,
-    "SVSTATE": 1,
-
-    "CR": 4,
-    "CA": 5,
-    "CA32": 6,
+    "CR": 0,
+    "LR": 0,
+    "CTR": 0,
+    "TAR": 0,
+    "MSR": 0,
+    "SVSTATE": 0,
+
+    "CA": 0,
+    "CA32": 0,
 
     "overflow": 7, # should definitely be last
 }