From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 13 Jan 2020 16:39:23 +0000 (+0100)
Subject: tools/litex_sim: use default integrated_rom_size
X-Git-Tag: 24jan2021_ls180~748
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1606dbc7252804af445af12e5130a387950553f;p=litex.git

tools/litex_sim: use default integrated_rom_size
---

diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py
index 99a0e169..ecf3edf6 100755
--- a/litex/tools/litex_sim.py
+++ b/litex/tools/litex_sim.py
@@ -107,7 +107,6 @@ class SimSoC(SoCSDRAM):
 
         # SoCSDRAM ---------------------------------------------------------------------------------
         SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
-            integrated_rom_size = 0x8000,
             ident               = "LiteX Simulation", ident_version=True,
             with_uart           = False,
             **kwargs)