From: Florent Kermarrec Date: Mon, 13 Apr 2015 11:37:46 +0000 (+0200) Subject: litescope: pep8 (E225) X-Git-Tag: 24jan2021_ls180~2354 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f16623d5486e1dfceeac035529340515eb7e3a47;p=litex.git litescope: pep8 (E225) --- diff --git a/misoclib/tools/litescope/bridge/uart2wb.py b/misoclib/tools/litescope/bridge/uart2wb.py index 2a494147..ccbf1331 100644 --- a/misoclib/tools/litescope/bridge/uart2wb.py +++ b/misoclib/tools/litescope/bridge/uart2wb.py @@ -27,7 +27,7 @@ class UARTMux(Module): # when sel==0, route it to shared rx and bridge rx # when sel==1, route it only to bridge rx self.comb += \ - If(self.sel==0, + If(self.sel == 0, self.shared_pads.rx.eq(pads.rx), self.bridge_pads.rx.eq(pads.rx) ).Else( @@ -38,7 +38,7 @@ class UARTMux(Module): # when sel==0, route shared tx to pads tx # when sel==1, route bridge tx to pads tx self.comb += \ - If(self.sel==0, + If(self.sel == 0, pads.tx.eq(self.shared_pads.tx) ).Else( pads.tx.eq(self.bridge_pads.tx) diff --git a/misoclib/tools/litescope/example_designs/test/test_io.py b/misoclib/tools/litescope/example_designs/test/test_io.py index 9938480b..ec6a9fae 100644 --- a/misoclib/tools/litescope/example_designs/test/test_io.py +++ b/misoclib/tools/litescope/example_designs/test/test_io.py @@ -32,6 +32,6 @@ def main(wb): ### led_anim0(io) led_anim1(io) - print("%02X" %io.read()) + print("{:02X}".format(io.read())) ### wb.close() diff --git a/misoclib/tools/litescope/host/driver/etherbone.py b/misoclib/tools/litescope/host/driver/etherbone.py index d094bde1..f7c5285a 100644 --- a/misoclib/tools/litescope/host/driver/etherbone.py +++ b/misoclib/tools/litescope/host/driver/etherbone.py @@ -54,7 +54,7 @@ class LiteScopeEtherboneDriver: datas = packet.records.pop().writes.get_datas() if self.debug: for i, data in enumerate(datas): - print("RD %08X @ %08X" %(data, addr + 4*(i%to_int(burst_length)))) + print("RD {:08X} @ {:08X}".format(data, addr + 4*(i%to_int(burst_length)))) return datas def write(self, addr, datas): @@ -82,4 +82,4 @@ class LiteScopeEtherboneDriver: if self.debug: for i, data in enumerate(datas): - print("WR %08X @ %08X" %(data, addr + 4*i)) + print("WR {:08X} @ {:08X}".format(data, addr + 4*i)) diff --git a/misoclib/tools/litescope/host/driver/io.py b/misoclib/tools/litescope/host/driver/io.py index 45180c36..c8e3c3f0 100644 --- a/misoclib/tools/litescope/host/driver/io.py +++ b/misoclib/tools/litescope/host/driver/io.py @@ -7,7 +7,7 @@ class LiteScopeIODriver(): def build(self): for key, value in self.regs.d.items(): if self.name in key: - key = key.replace(self.name +"_", "") + key = key.replace(self.name + "_", "") setattr(self, key, value) def write(self, value): diff --git a/misoclib/tools/litescope/host/driver/truthtable.py b/misoclib/tools/litescope/host/driver/truthtable.py index 5147f16d..305fe330 100644 --- a/misoclib/tools/litescope/host/driver/truthtable.py +++ b/misoclib/tools/litescope/host/driver/truthtable.py @@ -41,7 +41,7 @@ def gen_truth_table(s): truth_table = [] for i in range(2**width): for j in range(width): - exec("%s = stim[j][i]" %operands[j]) + exec("{} = stim[j][i]".format(operands[j])) truth_table.append(eval(s) != 0) return truth_table diff --git a/misoclib/tools/litescope/host/driver/uart.py b/misoclib/tools/litescope/host/driver/uart.py index 877e7bf2..b7f86e3c 100644 --- a/misoclib/tools/litescope/host/driver/uart.py +++ b/misoclib/tools/litescope/host/driver/uart.py @@ -56,7 +56,7 @@ class LiteScopeUARTDriver: data = data << 8 data |= ord(self.uart.read()) if self.debug: - print("RD %08X @ %08X" %(data, (addr+j)*4)) + print("RD {:08X} @ {:08X}".format(data, (addr+j)*4)) datas.append(data) return datas @@ -78,11 +78,11 @@ class LiteScopeUARTDriver: write_b(self.uart, (dat & 0xff000000) >> 24) dat = dat << 8 if self.debug: - print("WR %08X @ %08X" %(data[i], (addr + i)*4)) + print("WR {:08X} @ {:08X}".format(data[i], (addr + i)*4)) else: dat = data for j in range(4): write_b(self.uart, (dat & 0xff000000) >> 24) dat = dat << 8 if self.debug: - print("WR %08X @ %08X" %(data, (addr * 4))) + print("WR {:08X} @ {:08X}".format(data, (addr * 4))) diff --git a/misoclib/tools/litescope/host/dump/__init__.py b/misoclib/tools/litescope/host/dump/__init__.py index 84a9896e..19f1ea4b 100644 --- a/misoclib/tools/litescope/host/dump/__init__.py +++ b/misoclib/tools/litescope/host/dump/__init__.py @@ -1,13 +1,13 @@ def dec2bin(d, nb=0): - if d=="x": + if d == "x": return "x"*nb - elif d==0: - b="0" + elif d == 0: + b = "0" else: - b="" - while d!=0: - b="01"[d&1]+b - d=d>>1 + b = "" + while d != 0: + b = "01"[d&1] + b + d = d >> 1 return b.zfill(nb) @@ -101,7 +101,7 @@ class Dump: self.vars.append(var) def add_from_layout(self, layout, var): - i=0 + i = 0 for s, n in layout: self.add(Var(s, n, var[i:i+n])) i += n diff --git a/misoclib/tools/litescope/host/dump/csv.py b/misoclib/tools/litescope/host/dump/csv.py index 601e3503..80a6d3bb 100644 --- a/misoclib/tools/litescope/host/dump/csv.py +++ b/misoclib/tools/litescope/host/dump/csv.py @@ -32,7 +32,7 @@ class CSVDump(Dump): else: r += dec2bin(var.val, var.width) r += ", " - r+= "\n" + r += "\n" return r def write(self, filename): diff --git a/misoclib/tools/litescope/host/dump/sigrok.py b/misoclib/tools/litescope/host/dump/sigrok.py index d84d90d7..15d6d0e9 100644 --- a/misoclib/tools/litescope/host/dump/sigrok.py +++ b/misoclib/tools/litescope/host/dump/sigrok.py @@ -52,7 +52,7 @@ samplerate = {} KHz for j, var in enumerate(reversed(self.vars)): data = data << 1 try: - data |= var.values[i] %2 + data |= var.values[i] % 2 except: pass datas.append(data) diff --git a/misoclib/tools/litescope/host/dump/vcd.py b/misoclib/tools/litescope/host/dump/vcd.py index 5db234f5..d3fd6d3e 100644 --- a/misoclib/tools/litescope/host/dump/vcd.py +++ b/misoclib/tools/litescope/host/dump/vcd.py @@ -87,7 +87,7 @@ class VCDDump(Dump): r += dec2bin(var.val, var.width) r += " " r += var.vcd_id - r+= "\n" + r += "\n" r += "$end\n" return r