From: Tobias Platen <tplaten@posteo.de>
Date: Fri, 17 Apr 2020 16:06:25 +0000 (+0000)
Subject: add with carry instructions
X-Git-Tag: div_pipeline~1432^2~1
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f17100d6c435aec47b17acb188272a7e9b3cf67d;p=soc.git

add with carry instructions
---

diff --git a/src/soc/simulator/internalop_sim.py b/src/soc/simulator/internalop_sim.py
index 8f6a6421..726124a3 100644
--- a/src/soc/simulator/internalop_sim.py
+++ b/src/soc/simulator/internalop_sim.py
@@ -100,6 +100,8 @@ class InternalOpSimulator:
             return op1 & op2
         elif internal_op == InternalOp.OP_OR.value:
             return op1 | op2
+        elif internal_op == InternalOp.OP_MUL_L64.value:
+            return op1 * op2
         else:
             assert False, "Not implemented"
 
@@ -134,10 +136,20 @@ class InternalOpSimulator:
         if cry_in == CryIn.ONE.value:
             carry = 1
         elif cry_in == CryIn.CA.value:
-            carry = TODO # deliberately cause error here
+            carry = self.carry_out
 
         result = self.execute_alu_op(operand1, operand2, internal_op,
                                      carry=carry)
+
+        cry_out = yield pdecode2.dec.op.cry_out
+        ## TODO   yield pdecode2.dec.op.rc
+        if(cry_out==1):
+            if(result > 0xFFFFFFFF):
+                self.carry_out = 1
+            else:
+                self.carry_out = 0
+            
+            
         ro_ok = yield pdecode2.e.write_reg.ok
         if ro_ok:
             ro_sel = yield pdecode2.e.write_reg.data