From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 24 Jan 2020 02:56:06 +0000 (-0800)
Subject: abc9_ops: -prep_xaiger to skip (* keep *) cells
X-Git-Tag: working-ls180~849^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f180dba753c9f4bfb3b89575b0d224c73a1e8897;p=yosys.git

abc9_ops: -prep_xaiger to skip (* keep *) cells
---

diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc
index 750f36ceb..40622ece7 100644
--- a/passes/techmap/abc9_ops.cc
+++ b/passes/techmap/abc9_ops.cc
@@ -165,6 +165,8 @@ void prep_xaiger(RTLIL::Module *module, bool dff)
 	for (auto cell : module->cells()) {
 		if (cell->type == "$__ABC9_FF_")
 			continue;
+		if (cell->has_keep_attr())
+			continue;
 
 		auto inst_module = module->design->module(cell->type);
 		bool abc9_box = inst_module && inst_module->attributes.count("\\abc9_box_id");