From: Gabe Black <gabeblack@google.com>
Date: Wed, 19 Aug 2020 09:15:09 +0000 (-0700)
Subject: arch: Eliminate the unused HasUnalignedMemAcc constant.
X-Git-Tag: v20.1.0.0~264
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1840c9951408b25340ad6f383143f1018003d23;p=gem5.git

arch: Eliminate the unused HasUnalignedMemAcc constant.

Change-Id: Iaf9346df57336216c09979fe1d931701c6b7ddf6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32923
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/arm/isa_traits.hh b/src/arch/arm/isa_traits.hh
index 0ce38bcc9..2f8b634df 100644
--- a/src/arch/arm/isa_traits.hh
+++ b/src/arch/arm/isa_traits.hh
@@ -92,9 +92,6 @@ namespace ArmISA
 
     const uint32_t HighVecs = 0xFFFF0000;
 
-    // Memory accesses cannot be unaligned
-    const bool HasUnalignedMemAcc = true;
-
     enum InterruptTypes
     {
         INT_RST,
diff --git a/src/arch/mips/isa_traits.hh b/src/arch/mips/isa_traits.hh
index 9b44d8649..b97828fef 100644
--- a/src/arch/mips/isa_traits.hh
+++ b/src/arch/mips/isa_traits.hh
@@ -136,8 +136,6 @@ enum mode_type
 const int ANNOTE_NONE = 0;
 const uint32_t ITOUCH_ANNOTE = 0xffffffff;
 
-const bool HasUnalignedMemAcc = true;
-
 } // namespace MipsISA
 
 #endif // __ARCH_MIPS_ISA_TRAITS_HH__
diff --git a/src/arch/power/isa_traits.hh b/src/arch/power/isa_traits.hh
index 89bfa6bb5..0c82af2e0 100644
--- a/src/arch/power/isa_traits.hh
+++ b/src/arch/power/isa_traits.hh
@@ -54,9 +54,6 @@ const Addr PteMask = NPtePage - 1;
 
 const int MachineBytes = 4;
 
-// Memory accesses can be unaligned
-const bool HasUnalignedMemAcc = true;
-
 } // namespace PowerISA
 
 #endif // __ARCH_POWER_ISA_TRAITS_HH__
diff --git a/src/arch/riscv/isa_traits.hh b/src/arch/riscv/isa_traits.hh
index 8ba2e0cdc..a228a9071 100644
--- a/src/arch/riscv/isa_traits.hh
+++ b/src/arch/riscv/isa_traits.hh
@@ -54,9 +54,6 @@ const ByteOrder GuestByteOrder = LittleEndianByteOrder;
 const Addr PageShift = 12;
 const Addr PageBytes = ULL(1) << PageShift;
 
-// Memory accesses can be unaligned (at least for double-word memory accesses)
-const bool HasUnalignedMemAcc = true;
-
 }
 
 #endif //__ARCH_RISCV_ISA_TRAITS_HH__
diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 798910762..ad9cf0881 100644
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -44,9 +44,6 @@ const Addr PageBytes = ULL(1) << PageShift;
 
 StaticInstPtr decodeInst(ExtMachInst);
 
-// Memory accesses cannot be unaligned
-const bool HasUnalignedMemAcc = false;
-
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__
diff --git a/src/arch/x86/isa_traits.hh b/src/arch/x86/isa_traits.hh
index 98a2dc843..1f7a590b8 100644
--- a/src/arch/x86/isa_traits.hh
+++ b/src/arch/x86/isa_traits.hh
@@ -49,9 +49,6 @@ namespace X86ISA
 
     const Addr PageShift = 12;
     const Addr PageBytes = ULL(1) << PageShift;
-
-    // Memory accesses can be unaligned
-    const bool HasUnalignedMemAcc = true;
 }
 
 #endif // __ARCH_X86_ISATRAITS_HH__