From: Iago Toral Quiroga Date: Tue, 21 Nov 2017 10:33:53 +0000 (+0100) Subject: i965/vec4: fix splitting of interleaved attributes X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1873956dbbde78a9e4fb2df3cd2049891740bba;p=mesa.git i965/vec4: fix splitting of interleaved attributes When we split an instruction that reads an uniform value (vstride 0) we need to respect the vstride on the second half of the instruction (that is, the second half should read the same region as the first). We were doing this already, but we didn't account for stages that have interleaved input attributes which also have a vstride of 0 and need the same treatment. Fixes the following on Haswell: KHR-GL45.enhanced_layouts.varying_locations KHR-GL45.enhanced_layouts.varying_array_locations KHR-GL45.enhanced_layouts.varying_structure_locations Reviewed-by: Matt Turner Acked-by: Andres Gomez --- diff --git a/src/intel/compiler/brw_vec4.cpp b/src/intel/compiler/brw_vec4.cpp index bbe4585e0c7..73c40ad6009 100644 --- a/src/intel/compiler/brw_vec4.cpp +++ b/src/intel/compiler/brw_vec4.cpp @@ -2238,7 +2238,12 @@ vec4_visitor::lower_simd_width() if (linst->src[i].file == BAD_FILE) continue; - if (!is_uniform(linst->src[i])) + bool is_interleaved_attr = + linst->src[i].file == ATTR && + stage_uses_interleaved_attributes(stage, + prog_data->dispatch_mode); + + if (!is_uniform(linst->src[i]) && !is_interleaved_attr) linst->src[i] = horiz_offset(linst->src[i], channel_offset); }