From: Marek Olšák Date: Mon, 19 Apr 2010 22:50:39 +0000 (+0200) Subject: r300g: add is_rv350 flag X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f189caeed046e05bfeec8adf2ebeaae01d1bf2f6;p=mesa.git r300g: add is_rv350 flag --- diff --git a/src/gallium/drivers/r300/r300_chipset.c b/src/gallium/drivers/r300/r300_chipset.c index c77e944b6d9..928a310bd81 100644 --- a/src/gallium/drivers/r300/r300_chipset.c +++ b/src/gallium/drivers/r300/r300_chipset.c @@ -371,4 +371,6 @@ void r300_parse_chipset(struct r300_capabilities* caps) fprintf(stderr, "r300: Warning: Unknown chipset 0x%x\n", caps->pci_id); } + + caps->is_rv350 = caps->family >= CHIP_FAMILY_RV350; } diff --git a/src/gallium/drivers/r300/r300_chipset.h b/src/gallium/drivers/r300/r300_chipset.h index ff957b7c29c..ab649c38573 100644 --- a/src/gallium/drivers/r300/r300_chipset.h +++ b/src/gallium/drivers/r300/r300_chipset.h @@ -42,18 +42,28 @@ struct r300_capabilities { unsigned num_tex_units; /* Whether or not TCL is physically present */ boolean has_tcl; - /* Whether or not this is R400. The differences compared to their R3xx + /* Whether or not this is RV350 or newer, including all r400 and r500 + * chipsets. The differences compared to the oldest r300 chips are: + * - Blend LTE/GTE thresholds + * - Better MACRO_SWITCH in texture tiling + * - Half float vertex + * - More HyperZ optimizations */ + boolean is_rv350; + /* Whether or not this is R400. The differences compared their rv350 * cousins are: * - Extended fragment shader registers - * - Blend LTE/GTE thresholds */ + * - 3DC texture compression (RGTC2) */ boolean is_r400; /* Whether or not this is an RV515 or newer; R500s have many differences - * that require extra consideration, compared to their R3xx cousins: + * that require extra consideration, compared to their rv350 cousins: * - Extra bit of width and height on texture sizes * - Blend color is split across two registers - * - Blend LTE/GTE thresholds * - Universal Shader (US) block used for fragment shaders - * - FP16 blending and multisampling */ + * - FP16 blending and multisampling + * - Full RGTC texture compression + * - 24-bit depth textures + * - Stencil back-face reference value + * - Ability to render up to 2^24 - 1 vertices with signed index offset */ boolean is_r500; /* Whether or not the second pixel pipe is accessed with the high bit */ boolean high_second_pipe; diff --git a/src/gallium/drivers/r300/r300_state_invariant.c b/src/gallium/drivers/r300/r300_state_invariant.c index ffb175febf1..64d1d18b454 100644 --- a/src/gallium/drivers/r300/r300_state_invariant.c +++ b/src/gallium/drivers/r300/r300_state_invariant.c @@ -41,10 +41,9 @@ struct pipe_viewport_state r300_viewport_identity = { void r300_emit_invariant_state(struct r300_context* r300, unsigned size, void* state) { - struct r300_capabilities* caps = &r300_screen(r300->context.screen)->caps; CS_LOCALS(r300); - BEGIN_CS(12 + (caps->has_tcl ? 2: 0)); + BEGIN_CS(12 + (r300->screen->caps.has_tcl ? 2 : 0)); /*** Graphics Backend (GB) ***/ /* Subpixel multisampling for AA @@ -66,7 +65,7 @@ void r300_emit_invariant_state(struct r300_context* r300, /* Sign/normalize control */ OUT_CS_REG(R300_VAP_PSC_SGN_NORM_CNTL, R300_SGN_NORM_NO_ZERO); /* TCL-only stuff */ - if (caps->has_tcl) { + if (r300->screen->caps.has_tcl) { /* Amount of time to wait for vertex fetches in PVS */ OUT_CS_REG(VAP_PVS_VTX_TIMEOUT_REG, 0xffff); } @@ -74,10 +73,10 @@ void r300_emit_invariant_state(struct r300_context* r300, END_CS; /* XXX unsorted stuff from surface_fill */ - BEGIN_CS(38 + (caps->has_tcl ? 7 : 0) + - (caps->family >= CHIP_FAMILY_RV350 ? 4 : 0)); + BEGIN_CS(38 + (r300->screen->caps.has_tcl ? 7 : 0) + + (r300->screen->caps.is_rv350 ? 4 : 0)); - if (caps->has_tcl) { + if (r300->screen->caps.has_tcl) { /*Flushing PVS is required before the VAP_GB registers can be changed*/ OUT_CS_REG(R300_VAP_PVS_STATE_FLUSH_REG, 0); OUT_CS_REG_SEQ(R300_VAP_GB_VERT_CLIP_ADJ, 4); @@ -107,7 +106,7 @@ void r300_emit_invariant_state(struct r300_context* r300, OUT_CS_REG(R300_SC_EDGERULE, 0x2DA49525); OUT_CS_REG(R300_RB3D_AARESOLVE_CTL, 0x00000000); - if (caps->family >= CHIP_FAMILY_RV350) { + if (r300->screen->caps.is_rv350) { OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 0x01010101); OUT_CS_REG(R500_RB3D_DISCARD_SRC_PIXEL_GTE_THRESHOLD, 0xFEFEFEFE); } diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index e795c8df0bb..8bebeacf860 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -787,7 +787,7 @@ static void r300_setup_miptree(struct r300_screen* screen, { struct pipe_resource* base = &tex->b.b; unsigned stride, size, layer_size, nblocksy, i; - boolean rv350_mode = screen->caps.family >= CHIP_FAMILY_RV350; + boolean rv350_mode = screen->caps.is_rv350; SCREEN_DBG(screen, DBG_TEX, "r300: Making miptree for texture, format %s\n", util_format_name(base->format)); @@ -834,7 +834,7 @@ static void r300_setup_tiling(struct pipe_screen *screen, { struct r300_winsys_screen *rws = (struct r300_winsys_screen *)screen->winsys; enum pipe_format format = tex->b.b.format; - boolean rv350_mode = r300_screen(screen)->caps.family >= CHIP_FAMILY_RV350; + boolean rv350_mode = r300_screen(screen)->caps.is_rv350; boolean is_zb = util_format_is_depth_or_stencil(format); boolean dbg_no_tiling = SCREEN_DBG_ON(r300_screen(screen), DBG_NO_TILING);