From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 10 Jun 2019 23:16:40 +0000 (-0700)
Subject: If d_bit already in sigbit_chain_next, create extra wire
X-Git-Tag: yosys-0.9~53^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f19aa8d989df9e443d26cf6beaf389c2f3d6a424;p=yosys.git

If d_bit already in sigbit_chain_next, create extra wire
---

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index 21dfe9619..46f6a79fb 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -293,10 +293,13 @@ struct ShregmapWorker
 
 				if (opts.init || sigbit_init.count(q_bit) == 0)
 				{
-					if (sigbit_chain_next.count(d_bit)) {
+					auto r = sigbit_chain_next.insert(std::make_pair(d_bit, cell));
+					if (!r.second) {
 						sigbit_with_non_chain_users.insert(d_bit);
-					} else
-						sigbit_chain_next[d_bit] = cell;
+						Wire *wire = module->addWire(NEW_ID);
+						module->connect(wire, d_bit);
+						sigbit_chain_next.insert(std::make_pair(wire, cell));
+					}
 
 					sigbit_chain_prev[q_bit] = cell;
 					continue;