From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Fri, 8 May 2020 09:54:51 +0000 (+0200)
Subject: integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
X-Git-Tag: 24jan2021_ls180~372
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1a50a21388f5b6cabfa3bf0c481feade73957b9;p=litex.git

integration/soc: add add_uartbone method (to add a UARTBone aka UART Wishbone bridge).
---

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index e6315016..07fdac30 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -239,11 +239,13 @@ class UART(Module, AutoCSR, UARTInterface):
             self.ev.rx.trigger.eq(~rx_fifo.source.valid)
         ]
 
-class UARTWishboneBridge(WishboneStreamingBridge):
+class UARTBone(WishboneStreamingBridge):
     def __init__(self, pads, clk_freq, baudrate=115200):
         self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
         WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
 
+class UARTWishboneBridge(UARTBone): pass
+
 # UART Multiplexer ---------------------------------------------------------------------------------
 
 class UARTMultiplexer(Module):
diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 8d510762..d45b32fd 100644
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -926,13 +926,9 @@ class LiteXSoC(SoC):
             if name == "stub":
                 self.comb += self.uart.sink.ready.eq(1)
 
-        # Bridge
-        elif name in ["bridge"]:
-            self.submodules.uart = uart.UARTWishboneBridge(
-                pads     = self.platform.request("serial"),
-                clk_freq = self.sys_clk_freq,
-                baudrate = baudrate)
-            self.bus.add_master(name="uart_bridge", master=self.uart.wishbone)
+        # UARTBone / Bridge
+        elif name in ["uartbone", "bridge"]:
+            self.add_uartbone(baudrate=baudrate)
 
         # Crossover
         elif name in ["crossover"]:
@@ -986,6 +982,15 @@ class LiteXSoC(SoC):
         else:
             self.add_constant("UART_POLLING")
 
+    # Add UARTbone ---------------------------------------------------------------------------------
+    def add_uartbone(self, name="serial", baudrate=115200):
+        from litex.soc.cores import uart
+        self.submodules.uartbone = uart.UARTBone(
+            pads     = self.platform.request(name),
+            clk_freq = self.sys_clk_freq,
+            baudrate = baudrate)
+        self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
+
     # Add SDRAM ------------------------------------------------------------------------------------
     def add_sdram(self, name, phy, module, origin, size=None,
         l2_cache_size           = 8192,