From: Luke Kenneth Casson Leighton Date: Thu, 18 Oct 2018 22:53:53 +0000 (+0100) Subject: put sv_mmu override class in place X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1ab8918464ae410cfe06a449a8b8de2aaab26c7;p=riscv-isa-sim.git put sv_mmu override class in place --- diff --git a/dummy_rocc/dummy_rocc.cc b/dummy_rocc/dummy_rocc.cc index 85ab7aa..7148aa8 100644 --- a/dummy_rocc/dummy_rocc.cc +++ b/dummy_rocc/dummy_rocc.cc @@ -22,7 +22,11 @@ class dummy_rocc_t : public rocc_t case 1: // xd <- acc (the only real work is the return statement below) break; case 2: // acc[rs2] <- Mem[xs1] - acc[insn.rs2] = p->get_mmu()->load_uint64(xs1); + acc[insn.rs2] = p->get_mmu()->load_uint64(xs1) +#ifdef NOT_SPIKE_SIMPLEV + .get_data() +#endif +; break; case 3: // acc[rs2] <- accX + xs1 acc[insn.rs2] += xs1; diff --git a/riscv/debug_module.cc b/riscv/debug_module.cc index 96de3c8..4cf8669 100644 --- a/riscv/debug_module.cc +++ b/riscv/debug_module.cc @@ -274,13 +274,29 @@ void debug_module_t::sb_read() reg_t address = ((uint64_t) sbaddress[1] << 32) | sbaddress[0]; try { if (sbcs.sbaccess == 0 && max_bus_master_bits >= 8) { - sbdata[0] = sim->debug_mmu->load_uint8(address); + sbdata[0] = sim->debug_mmu->load_uint8(address) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif +; } else if (sbcs.sbaccess == 1 && max_bus_master_bits >= 16) { - sbdata[0] = sim->debug_mmu->load_uint16(address); + sbdata[0] = sim->debug_mmu->load_uint16(address) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif +; } else if (sbcs.sbaccess == 2 && max_bus_master_bits >= 32) { - sbdata[0] = sim->debug_mmu->load_uint32(address); + sbdata[0] = sim->debug_mmu->load_uint32(address) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif +; } else if (sbcs.sbaccess == 3 && max_bus_master_bits >= 64) { - uint64_t value = sim->debug_mmu->load_uint64(address); + uint64_t value = sim->debug_mmu->load_uint64(address) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif +; sbdata[0] = value; sbdata[1] = value >> 32; } else { diff --git a/riscv/execute.cc b/riscv/execute.cc index e639e90..eb8c79c 100644 --- a/riscv/execute.cc +++ b/riscv/execute.cc @@ -103,7 +103,11 @@ void processor_t::step(size_t n) while (n > 0) { size_t instret = 0; reg_t pc = state.pc; +#ifdef SPIKE_SIMPLEV + sv_mmu_t* _mmu = mmu; +#else mmu_t* _mmu = mmu; +#endif #define advance_pc() \ if (unlikely(invalid_pc(pc))) { \ diff --git a/riscv/interactive.cc b/riscv/interactive.cc index b645c29..2840963 100644 --- a/riscv/interactive.cc +++ b/riscv/interactive.cc @@ -3,7 +3,11 @@ #include "decode.h" #include "disasm.h" #include "sim.h" +#ifdef SPIKE_SIMPLEV +#include "sv_mmu.h" +#else #include "mmu.h" +#endif #include #include #include @@ -264,7 +268,11 @@ reg_t sim_t::get_mem(const std::vector& args) throw trap_interactive(); std::string addr_str = args[0]; +#ifdef SPIKE_SIMPLEV + sv_mmu_t* mmu = debug_mmu; +#else mmu_t* mmu = debug_mmu; +#endif if(args.size() == 2) { processor_t *p = get_core(args[0]); @@ -279,17 +287,33 @@ reg_t sim_t::get_mem(const std::vector& args) switch(addr % 8) { case 0: - val = mmu->load_uint64(addr); + val = mmu->load_uint64(addr) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif + ; break; case 4: - val = mmu->load_uint32(addr); + val = mmu->load_uint32(addr) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif + ; break; case 2: case 6: - val = mmu->load_uint16(addr); + val = mmu->load_uint16(addr) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif + ; break; default: - val = mmu->load_uint8(addr); + val = mmu->load_uint8(addr) +#ifdef NOTYET_SPIKE_SIMPLEV + .get_data() +#endif + ; break; } return val; @@ -308,8 +332,13 @@ void sim_t::interactive_str(const std::string& cmd, const std::vectorload_uint8(addr++).get_data())) + putchar(ch); +#else while((ch = debug_mmu->load_uint8(addr++))) putchar(ch); +#endif putchar('\n'); } diff --git a/riscv/mmu.h b/riscv/mmu.h index 3f111a3..0bcfb3c 100644 --- a/riscv/mmu.h +++ b/riscv/mmu.h @@ -393,4 +393,8 @@ inline vm_info decode_vm_info(int xlen, reg_t prv, reg_t satp) } } +#ifdef SPIKE_SIMPLEV +#include "sv_mmu.h" +#endif + #endif diff --git a/riscv/processor.cc b/riscv/processor.cc index 3586dc0..a7f6a92 100644 --- a/riscv/processor.cc +++ b/riscv/processor.cc @@ -33,7 +33,11 @@ processor_t::processor_t(const char* isa, simif_t* sim, uint32_t id, parse_isa_string(isa); register_base_instructions(); +#ifdef SPIKE_SIMPLEV + mmu = new sv_mmu_t(sim, this); +#else mmu = new mmu_t(sim, this); +#endif disassembler = new disassembler_t(max_xlen); if (ext) diff --git a/riscv/processor.h b/riscv/processor.h index 1ffdfab..41a1f22 100644 --- a/riscv/processor.h +++ b/riscv/processor.h @@ -17,6 +17,7 @@ class processor_t; class mmu_t; +class sv_mmu_t; typedef reg_t (*insn_func_t)(processor_t*, insn_t, reg_t); class simif_t; class trap_t; @@ -188,7 +189,11 @@ public: void step(size_t n); // run for n cycles void set_csr(int which, reg_t val); reg_t get_csr(int which); +#ifdef SPIKE_SIMPLEV + sv_mmu_t* get_mmu() { return mmu; } +#else mmu_t* get_mmu() { return mmu; } +#endif state_t* get_state() { return &state; } unsigned get_xlen() { return xlen; } unsigned get_max_xlen() { return max_xlen; } @@ -313,7 +318,11 @@ public: private: simif_t* sim; +#ifdef SPIKE_SIMPLEV + sv_mmu_t* mmu; +#else mmu_t* mmu; // main memory is always accessed via the mmu +#endif extension_t* ext; disassembler_t* disassembler; state_t state; @@ -339,6 +348,9 @@ private: void enter_debug_mode(uint8_t cause); +#ifdef SPIKE_SIMPLEV + friend class sv_mmu_t; +#endif friend class mmu_t; friend class clint_t; friend class extension_t; diff --git a/riscv/sim.cc b/riscv/sim.cc index 44223a7..de57edf 100644 --- a/riscv/sim.cc +++ b/riscv/sim.cc @@ -41,7 +41,11 @@ sim_t::sim_t(const char* isa, size_t nprocs, bool halted, reg_t start_pc, debug_module.add_device(&bus); +#ifdef SPIKE_SIMPLEV + debug_mmu = new sv_mmu_t(this, NULL); +#else debug_mmu = new mmu_t(this, NULL); +#endif if (hartids.size() == 0) { for (size_t i = 0; i < procs.size(); i++) { diff --git a/riscv/sim.h b/riscv/sim.h index b847bdb..2a5df26 100644 --- a/riscv/sim.h +++ b/riscv/sim.h @@ -13,7 +13,11 @@ #include #include +#ifdef SPIKE_SIMPLEV +class sv_mmu_t; +#else class mmu_t; +#endif class remote_bitbang_t; // this class encapsulates the processors and memory in a RISC-V machine. @@ -47,7 +51,11 @@ public: private: std::vector> mems; +#ifdef SPIKE_SIMPLEV + sv_mmu_t* debug_mmu; +#else mmu_t* debug_mmu; // debug port into main memory +#endif std::vector procs; reg_t start_pc; std::string dts;