From: Andre Vieira Date: Mon, 15 Apr 2019 10:29:14 +0000 (+0100) Subject: [binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1c7f42126274d48f6b0a929e4e15a32193997c6;p=binutils-gdb.git [binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M Mainline This patch is part of a series of patches to add support for Armv8.1-M Mainline instructions to binutils. This patch adds the BFX and BFLX instructions. ChangeLog entries are as follows : *** gas/ChangeLog *** 2019-04-15 Sudakshina Das * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. (do_t_v8_1_branch): New switch cases for bfx and bflx. (insns): New instruction for bfx and bflx. * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New *** opcodes/ChangeLog *** 2019-04-15 Sudakshina Das * arm-dis.c (print_insn_thumb32): Add '%S' to print an Arm register with r13 and r15 unpredictable. (thumb32_opcodes): New instructions for bfx and bflx. --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 493a59feb95..10aa75768c6 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,14 @@ +2019-04-15 Sudakshina Das + + * config/tc-arm.c (T16_32_TAB): New entries for bfx and bflx. + (do_t_v8_1_branch): New switch cases for bfx and bflx. + (insns): New instruction for bfx and bflx. + * testsuite/gas/arm/armv8_1-m-bf-exchange.d: New. + * testsuite/gas/arm/armv8_1-m-bf-exchange.s: New. + * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s: New + * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l: New + * testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d: New + 2019-04-15 Sudakshina Das Andre Vieira diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index caba2736c16..c7c1a82a998 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -10506,6 +10506,8 @@ encode_thumb32_addr_mode (int i, bfd_boolean is_t, bfd_boolean is_d) X(_b, e000, f000b000), \ X(_bcond, d000, f0008000), \ X(_bf, 0000, f040e001), \ + X(_bfx, 0000, f060e001), \ + X(_bflx, 0000, f070e001), \ X(_bic, 4380, ea200000), \ X(_bics, 4380, ea300000), \ X(_cmn, 42c0, eb100f00), \ @@ -13362,6 +13364,11 @@ do_t_branch_future (void) } break; + case T_MNEM_bfx: + case T_MNEM_bflx: + inst.instruction |= inst.operands[1].reg << 16; + break; + default: abort (); } } @@ -21679,6 +21686,8 @@ static const struct asm_opcode insns[] = #undef THUMB_VARIANT #define THUMB_VARIANT & arm_ext_v8_1m_main toC("bf", _bf, 2, (EXPs, EXPs), t_branch_future), + toC("bfx", _bfx, 2, (EXPs, RRnpcsp), t_branch_future), + toC("bflx", _bflx, 2, (EXPs, RRnpcsp), t_branch_future), }; #undef ARM_VARIANT #undef THUMB_VARIANT diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d new file mode 100644 index 00000000000..3ee7df81610 --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.d @@ -0,0 +1,4 @@ +#name: Invalid Armv8.1-M Mainline BF-exchange instructions +#source: armv8_1-m-bf-exchange-bad.s +#as: -march=armv8.1-m.main +#error_output: armv8_1-m-bf-exchange-bad.l diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l new file mode 100644 index 00000000000..1033b71e6ea --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.l @@ -0,0 +1,7 @@ +.*: Assembler messages: +.*:6: Error: branch out of range or not a multiple of 2 +.*:7: Error: branch out of range or not a multiple of 2 +.*:8: Error: branch out of range or not a multiple of 2 +.*:9: Error: branch out of range or not a multiple of 2 +.*:11: Error: r15 not allowed here -- `bfx 2,PC' +.*:12: Error: r13 not allowed here -- `bflx 2,SP' diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s new file mode 100644 index 00000000000..ca06eaf3d4f --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange-bad.s @@ -0,0 +1,12 @@ + .syntax unified + .text + .thumb +foo: + # OP0 : Unsigned, 5-bit, even + bfx 0, r3 + bfx -2, r3 + bflx 3, r3 + bflx 32, r3 + # OP1 : no SP or PC + bfx 2, PC + bflx 2, SP diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d new file mode 100644 index 00000000000..e88bb941acd --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.d @@ -0,0 +1,14 @@ +#name: Valid Armv8.1-M Mainline BF-exchange instructions +#source: armv8_1-m-bf-exchange.s +#as: -march=armv8.1-m.main +#objdump: -dr --prefix-addresses --show-raw-insn + +.*: +file format .*arm.* + +Disassembly of section .text: +0[0-9a-f]+ <[^>]+> f265 e001 bfx 8, r5 +0[0-9a-f]+ <[^>]+> 4609 mov r1, r1 +0[0-9a-f]+ <[^>]+> f173 e001 bflx 4, r3 +0[0-9a-f]+ <[^>]+> 460a mov r2, r1 +0[0-9a-f]+ <[^>]+> 4613 mov r3, r2 +0[0-9a-f]+ <[^>]+> 4614 mov r4, r2 diff --git a/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s new file mode 100644 index 00000000000..e3d9dfcdc7a --- /dev/null +++ b/gas/testsuite/gas/arm/armv8_1-m-bf-exchange.s @@ -0,0 +1,12 @@ + .syntax unified + .text + .thumb +foo: + bfx .LB1, r5 + mov r1, r1 + bflx .LB2, r3 + mov r2, r1 +.LB1: + mov r3, r2 +.LB2: + mov r4, r2 diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 3c782d11e87..e4de1d7305d 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2019-04-15 Sudakshina Das + + * arm-dis.c (print_insn_thumb32): Add '%S' to print an + Arm register with r13 and r15 unpredictable. + (thumb32_opcodes): New instructions for bfx and bflx. + 2019-04-15 Sudakshina Das * arm-dis.c (thumb32_opcodes): New instructions for bf. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index d4a9375a883..08af17193af 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -2730,6 +2730,7 @@ static const struct opcode16 thumb_opcodes[] = %W print bitfield*4 in decimal %r print bitfield as an ARM register %R as %<>r but r15 is UNPREDICTABLE + %S as %<>r but r13 and r15 is UNPREDICTABLE %c print bitfield as a condition code %'c print specified char iff bitfield is all ones @@ -2749,6 +2750,10 @@ static const struct opcode32 thumb32_opcodes[] = /* Armv8.1-M Mainline instructions. */ {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), 0xf040e001, 0xf860f001, "bf%c\t%G, %W"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf060e001, 0xf8f0f001, "bfx%c\t%G, %16-19S"}, + {ARM_FEATURE_CORE_HIGH (ARM_EXT2_V8_1M_MAIN), + 0xf070e001, 0xf8f0f001, "bflx%c\t%G, %16-19S"}, /* ARMv8-M and ARMv8-M Security Extensions instructions. */ @@ -6056,6 +6061,10 @@ print_insn_thumb32 (bfd_vma pc, struct disassemble_info *info, long given) value_in_comment = val * 4; break; + case 'S': + if (val == 13) + is_unpredictable = TRUE; + /* Fall through. */ case 'R': if (val == 15) is_unpredictable = TRUE;