From: lkcl <lkcl@web>
Date: Wed, 4 Aug 2021 15:09:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~500
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1d20cc7d26c02dc46a51727b5f65e19124938f8;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index ef0a9659b..7ec90552a 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -155,9 +155,7 @@ bitspace and so bit 16 has been chosen as `Rc`.
 **These interpretations are only available for sv.bc, they are NOT
 available for Power ISA v3.0B** i.e. only when embedded in an SVP64
 Prefix Context do these and all other parts of this specification
-apply.  To repeat: **Standard Scalar v3.0B Branch is in
-absolutely no way impacted or altered in any way shape or form by
-the SVP64 variant of the same**
+apply.
 
 Pseudocode for Rc in sv.bc