From: Alexander Ivchenko Date: Tue, 14 Oct 2014 08:13:31 +0000 (+0000) Subject: AVX-512. 58/n. Add vpmul[u]dq insn patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=f1df7a1c5210814e7580aaf7b2a71d8f9710cfbf;p=gcc.git AVX-512. 58/n. Add vpmul[u]dq insn patterns. gcc/ * config/i386/sse.md (define_expand "vec_widen_umult_even_v8si"): Add masking. (define_insn "*vec_widen_umult_even_v8si"): Ditto. (define_expand "vec_widen_umult_even_v4si"): Ditto. (define_insn "*vec_widen_umult_even_v4si"): Ditto. (define_expand "vec_widen_smult_even_v8si"): Ditto. (define_insn "*vec_widen_smult_even_v8si"): Ditto. (define_expand "sse4_1_mulv2siv2di3"): Ditto. (define_insn "*sse4_1_mulv2siv2di3"): Ditto. (define_insn "avx512dq_mul3"): New. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r216176 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 0a4673c98a8..604e34c0aef 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2014-10-14 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_expand "vec_widen_umult_even_v8si"): Add masking. + (define_insn "*vec_widen_umult_even_v8si"): Ditto. + (define_expand "vec_widen_umult_even_v4si"): Ditto. + (define_insn "*vec_widen_umult_even_v4si"): Ditto. + (define_expand "vec_widen_smult_even_v8si"): Ditto. + (define_insn "*vec_widen_smult_even_v8si"): Ditto. + (define_expand "sse4_1_mulv2siv2di3"): Ditto. + (define_insn "*sse4_1_mulv2siv2di3"): Ditto. + (define_insn "avx512dq_mul3"): New. + 2014-10-14 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index d544ed0676e..70cfa6a99ab 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -9173,7 +9173,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "vec_widen_umult_even_v8si" +(define_expand "vec_widen_umult_even_v8si" [(set (match_operand:V4DI 0 "register_operand") (mult:V4DI (zero_extend:V4DI @@ -9186,29 +9186,30 @@ (match_operand:V8SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2" + "TARGET_AVX2 && " "ix86_fixup_binary_operands_no_copy (MULT, V8SImode, operands);") -(define_insn "*vec_widen_umult_even_v8si" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "*vec_widen_umult_even_v8si" + [(set (match_operand:V4DI 0 "register_operand" "=v") (mult:V4DI (zero_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "%x") + (match_operand:V8SI 1 "nonimmediate_operand" "%v") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (zero_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 2 "nonimmediate_operand" "xm") + (match_operand:V8SI 2 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V8SImode, operands)" - "vpmuludq\t{%2, %1, %0|%0, %1, %2}" + "TARGET_AVX2 && + && ix86_binary_operator_ok (MULT, V8SImode, operands)" + "vpmuludq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_expand "vec_widen_umult_even_v4si" +(define_expand "vec_widen_umult_even_v4si" [(set (match_operand:V2DI 0 "register_operand") (mult:V2DI (zero_extend:V2DI @@ -9219,28 +9220,29 @@ (vec_select:V2SI (match_operand:V4SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_SSE2" + "TARGET_SSE2 && " "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") -(define_insn "*vec_widen_umult_even_v4si" - [(set (match_operand:V2DI 0 "register_operand" "=x,x") +(define_insn "*vec_widen_umult_even_v4si" + [(set (match_operand:V2DI 0 "register_operand" "=x,v") (mult:V2DI (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "%0,x") + (match_operand:V4SI 1 "nonimmediate_operand" "%0,v") (parallel [(const_int 0) (const_int 2)]))) (zero_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm") (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)" + "TARGET_SSE2 && + && ix86_binary_operator_ok (MULT, V4SImode, operands)" "@ pmuludq\t{%2, %0|%0, %2} - vpmuludq\t{%2, %1, %0|%0, %1, %2}" + vpmuludq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseimul") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "TI")]) (define_expand "vec_widen_smult_even_v16si" @@ -9288,7 +9290,7 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_expand "vec_widen_smult_even_v8si" +(define_expand "vec_widen_smult_even_v8si" [(set (match_operand:V4DI 0 "register_operand") (mult:V4DI (sign_extend:V4DI @@ -9301,30 +9303,31 @@ (match_operand:V8SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2" + "TARGET_AVX2 && " "ix86_fixup_binary_operands_no_copy (MULT, V8SImode, operands);") -(define_insn "*vec_widen_smult_even_v8si" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "*vec_widen_smult_even_v8si" + [(set (match_operand:V4DI 0 "register_operand" "=v") (mult:V4DI (sign_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 1 "nonimmediate_operand" "x") + (match_operand:V8SI 1 "nonimmediate_operand" "v") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)]))) (sign_extend:V4DI (vec_select:V4SI - (match_operand:V8SI 2 "nonimmediate_operand" "xm") + (match_operand:V8SI 2 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 2) (const_int 4) (const_int 6)])))))] - "TARGET_AVX2 && ix86_binary_operator_ok (MULT, V8SImode, operands)" - "vpmuldq\t{%2, %1, %0|%0, %1, %2}" + "TARGET_AVX2 + && ix86_binary_operator_ok (MULT, V8SImode, operands)" + "vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "type" "sseimul") (set_attr "prefix_extra" "1") (set_attr "prefix" "vex") (set_attr "mode" "OI")]) -(define_expand "sse4_1_mulv2siv2di3" +(define_expand "sse4_1_mulv2siv2di3" [(set (match_operand:V2DI 0 "register_operand") (mult:V2DI (sign_extend:V2DI @@ -9335,24 +9338,25 @@ (vec_select:V2SI (match_operand:V4SI 2 "nonimmediate_operand") (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_SSE4_1" + "TARGET_SSE4_1 && " "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);") -(define_insn "*sse4_1_mulv2siv2di3" - [(set (match_operand:V2DI 0 "register_operand" "=x,x") +(define_insn "*sse4_1_mulv2siv2di3" + [(set (match_operand:V2DI 0 "register_operand" "=x,v") (mult:V2DI (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "%0,x") + (match_operand:V4SI 1 "nonimmediate_operand" "%0,v") (parallel [(const_int 0) (const_int 2)]))) (sign_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 2 "nonimmediate_operand" "xm,xm") + (match_operand:V4SI 2 "nonimmediate_operand" "xm,vm") (parallel [(const_int 0) (const_int 2)])))))] - "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)" + "TARGET_SSE4_1 && + && ix86_binary_operator_ok (MULT, V4SImode, operands)" "@ pmuldq\t{%2, %0|%0, %2} - vpmuldq\t{%2, %1, %0|%0, %1, %2}" + vpmuldq\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseimul") (set_attr "prefix_data16" "1,*") @@ -9491,6 +9495,17 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) +(define_insn "avx512dq_mul3" + [(set (match_operand:VI8 0 "register_operand" "=v") + (mult:VI8 + (match_operand:VI8 1 "register_operand" "v") + (match_operand:VI8 2 "nonimmediate_operand" "vm")))] + "TARGET_AVX512DQ && " + "vpmullq\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sseimul") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_expand "mul3" [(set (match_operand:VI4_AVX512F 0 "register_operand") (mult:VI4_AVX512F